Freescale Semiconductor MPC5604B - Page 369

MPC5604B/C Microcontroller Reference Manual, Rev. 8
358 Freescale Semiconductor
20.3.3 I
2
C Bus Frequency Divider Register (IBFD)
Offset 0x1 Access: Read/write any time
76543210
R
IBC
W
Reset00000000
Figure 20-3. I
2
C Bus Frequency Divider Register (IBFD)
Table 20-3. IBFD field descriptions
Field Description
IBC I-Bus Clock Rate. This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider. The IBC bits are decoded to give the Tap and Prescale values as
follows:
7–6 select the prescaled shift register (see Ta bl e 2 0-4)
5–3 select the prescaler divider (see Ta ble 2 0-5)
2–0 select the shift register tap point (see Table 20-6)
Table 20-4. I-Bus multiplier factor
IBC7–6MUL
00 01
01 02
10 04
11 RESERVED
Table 20-5. I-Bus prescaler divider values
IBC5–3
scl2start
(clocks)
scl2stop
(clocks)
scl2tap
(clocks)
tap2tap
(clocks)
0002741
0012742
0102964
0116968
100 14 17 14 16
101 30 33 30 32
110 62 65 62 64
111 126 129 126 128