MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 441
there is no message on the bus, it counts using the previously programmed baud rate. During Freeze Mode,
the timer is not incremented.
The timer value is captured at the beginning of the identifier field of any frame on the CAN bus. This
captured value is written into the Time Stamp entry in a message buffer after a successful reception or
transmission of a message.
Writing to the timer is an indirect operation. The data is first written to an auxiliary register and then an
internal request/acknowledge procedure across clock domains is executed. All this is transparent to the
user, except for the fact that the data will take some time to be actually written to the register. If desired,
software can poll the register to discover when the data was actually written.
22.3.4.4 Rx Global Mask (RXGMASK)
This register is provided for legacy support and for low cost MCUs that do not have the individual masking
per Message Buffer feature. For MCUs supporting individual masks per MB, setting the BCC bit in MCR
causes the RXGMASK Register to have no effect on the module operation. For MCUs not supporting
individual masks per MB, this register is always effective.
RXGMASK is used as acceptance mask for all Rx MBs, excluding MBs 14
–15, which have individual
mask registers. When the FEN bit in MCR is set (FIFO enabled), the RXGMASK also applies to all
elements of the ID filter table, except elements 6–7, which have individual masks.
Refer to Section 22.4.8, “Rx FIFO for important details on usage of RXGMASK on filtering process for
Rx FIFO.
The contents of this register must be programmed while the module is in Freeze Mode, and must not be
modified when the module is transmitting or receiving frames.
Offset: 0x0008 Access: Read/write
0123456789101112131415
R0000000000000000
W
Reset
0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
TIMER
W
Reset
0000000000000000
Figure 22-7. Free Running Timer (TIMER)
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