MPC5604B/C Microcontroller Reference Manual, Rev. 8
766 Freescale Semiconductor
by a module input signal; it can only be read from the IPS programming model. Any attempted write is
ignored.
31.4.2.4 Miscellaneous Wakeup Control Register (MWCR)
Implementation of low-power sleep modes and exit from these modes via an interrupt require
communication between the ECSM, the interrupt controller and off-platform external logic typically
associated with phase-locked loop clock generation circuitry. The Miscellaneous Wakeup Control Register
(MWCR) provides an 8-bit register controlling entry into these types of low-power modes as well as
definition of the interrupt level needed to exit the mode.
The following sequence of operations is generally needed to enable this functionality. Note that the exact
details are likely to be system-specific.
1. The processor core loads the appropriate data value into the MWCR, setting the ENBWCR bit and
the desired interrupt priority level.
2. At the appropriate time, the processor ceases execution. The exact mechanism varies by processor
core. In some cases, a processor-is-stopped status is signaled to the ECSM and off-platform
external logic. This assertion, if properly enabled by MWCR[ENBWCR], causes the ECSM output
signal “enter_low_power_mode” to be set. This, in turn, causes the selected off-platform external,
low-power mode, as specified by MWCR[LPMD], to be entered, and the appropriate clock signals
disabled. In most implementations, there are multiple low-power modes, where the exact clocks to
be disabled vary across the different modes.
Offset: 0x08 Access: Read
0123456789101112131415
R MC[31:16]
W
Reset:0000000000000011
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R MC[15:0]
W
Reset:0000000010000101
Figure 31-3. IPS On-Platform Module Configuration Register (IOPMC)
Table 31-4. IOPMC field descriptions
Field Description
MC IPS Module Configuration
MC[n] = 0 if an IPS module connection to decoded slot “n” is absent
MC[n] = 1 if an IPS module connection to decoded slot “n” is present
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