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USB on-the-go full-speed (OTG_FS) RM0402

1016/1163 RM0402 Rev 6

29.15.11 OTG status read and pop registers [alternate] (OTG_GRXSTSP)

Address offset for pop: 0x020

Reset value: 0x0000 0000

This description is for register OTG_GRXSTSP in Host mode.

Similarly to OTG_GRXSTSR (receive status debug read register) where a read returns the

contents of the top of the receive FIFO, a read to OTG_GRXSTSP (receive status read and

pop register) additionally pops the top data entry out of the Rx FIFO.

The core ignores the receive status pop/read when the receive FIFO is empty and returns a

value of 0x0000

0000. The application must only pop the receive status FIFO when the

receive FIFO non-empty bit of the core interrupt register (RXFLVL bit in OTG_GINTSTS) is

asserted.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PKTSTS[3:0] DPID

rrrrr

1514131211109876543210

DPID BCNT[10:0] CHNUM[3:0]

rrrrrrrrrrrrrrrr

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:17 PKTSTS[3:0]: Packet status

Indicates the status of the received packet

0010: IN data packet received

0011: IN transfer completed (triggers an interrupt)

0101: Data toggle error (triggers an interrupt)

0111: Channel halted (triggers an interrupt)

Others: Reserved

Bits 16:15 DPID[1:0]: Data PID

Indicates the data PID of the received packet

00: DATA0

10: DATA1

Bits 14:4 BCNT[10:0]: Byte count

Indicates the byte count of the received IN data packet.

Bits 3:0 CHNUM[3:0]: Channel number

Indicates the channel number to which the current received packet belongs.

ST STM32F412 User Manual

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