RM0402 Rev 6 277/1163
RM0402 Flexible static memory controller (FSMC)
287
Figure 50. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)
1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.
2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.
Addr[15:0] data
addr[25:16]
Memory transaction = burst of 2 half words
HCLK
CLK
A[25:16]
NEx
NOE
NWE
Hi-Z
NADV
NWAIT
(WAITCFG = 0)
A/D[15:0]
1 clock 1 clock
(DATLAT + 2)
inserted wait state
ai14731f
CLK cycles
data
Table 68. FSMC_BCRx bitfields (Synchronous multiplexed write mode)
Bit number Bit name Value to set
31:22 Reserved 0x000
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW 0x1
18:16 CPSIZE As needed (0x1 for CRAM 1.5)
15 ASYNCWAIT 0x0
14 EXTMOD 0x0
13 WAITEN
To be set to 1 if the memory supports this feature, to be kept at 0
otherwise.
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