ST STM32F412

Flexible static memory controller (FSMC) RM0402
258/1163 RM0402 Rev 6
Mode A - SRAM/PSRAM (CRAM) OE toggling
Figure 35. Mode A read access waveforms
1. NBL[1:0] are driven low during the read access
Figure 36. Mode A write access waveforms
A[25:0]
NOE
ADDSET DATAST
Memory transaction
NEx
D[15:0]
HCLK cycles HCLK cycles
NWE
NBL[1:0]
data driven
by memory
MS34479V1
High
A[25:0]
NOE
ADDSET (DATAST + 1)
Memory transaction
NEx
D[15:0]
HCLK cycles HCLK cycles
NWE
NBL[1:0]
data driven by FSMC
MS34480V1
1HCLK