Reset and clock control (RCC) for STM32F412xx RM0402
162/1163 RM0402 Rev 6
6.3.25 RCC clocks gated enable register (CKGATENR)
Address offset: 0x90
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
This register allows to enable or disable the clock gating for the specified IPs.
Bits 23: 16 Reserved, must be kept at reset value.
Bit 15 CKDFSDM1ASEL: DFSDM1 audio clock selection.
0: CK_I2S_APB1 selected as audio clock
1: CK_I2S_APB2 selected as audio clock
Bits 14:0 Reserved, must be kept at reset value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res.
EVTCL
_CKEN
RCC
_CKEN
FLITF
_CKEN
SRAM
_CKEN
SPARE
_CKEN
CM4DBG
_CKEN
AHB2APB2
_CKEN
AHB2APB1
_CKEN
rw rw rw rw rw rw rw rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 EVTCL_CKEN
0: the clock gating is enabled
1: the cock gating is disabled, the clock is always enabled
Bit 6
RCC_CKEN: RCC clock enable
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
Bit 5
FLITF_CKEN: Flash Interface clock enable
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
Bit 4
SRAM_CKEN: SRQAM controller clock enable
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
Bit 3
SPARE_CKEN: Spare clock enable
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
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