Digital filter for sigma delta modulators (DFSDM) RM0402
382/1163 RM0402 Rev 6
14.8 DFSDM filter x module registers (x=0..1)
Word access (32-bit) must be used for registers write access except DFSDM_CHyDATINR
register.
14.8.1 DFSDM filter x control register 1 (DFSDM_FLTxCR1)
Address offset: 0x100 + 0x80 * x, (x = 0 to 1)
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res.
AWF
SEL
FAST Res. Res. Res. RCH[1:0] Res. Res.
RDMA
EN
Res. RSYNC
RCON
T
RSW
START
Res.
rw rw rw rw rw rw rw rt_w1
1514131211109876543210
Res. JEXTEN[1:0] Res. Res. JEXTSEL[2:0] Res. Res.
JDMA
EN
JSCAN JSYNC Res.
JSW
START
DFEN
rw rw rw rw rw rw rw rw rt_w1 rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 AWFSEL: Analog watchdog fast mode select
0: Analog watchdog on data output value (after the digital filter). The comparison is done after offset
correction and shift
1: Analog watchdog on channel transceivers value (after watchdog filter)
Bit 29 FAST: Fast conversion mode selection for regular conversions
0: Fast conversion mode disabled
1: Fast conversion mode enabled
When converting a regular conversion in continuous mode, having enabled the fast mode causes
each conversion (except the first) to execute faster than in standard mode. This bit has no effect on
conversions which are not continuous.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [F
OSR
* (I
OSR
-1 + F
ORD
) + F
ORD
] / f
CKIN
..... for Sinc
x
filters
t = [F
OSR
* (I
OSR
-1 + 4) + 2] / f
CKIN
..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [F
OSR
* I
OSR
] / f
CKIN
in case if F
OSR
= F
OSR
[9:0]+1 = 1 (filter bypassed, active only integrator):
t = I
OSR
/ f
CKIN
(... but CNVCNT=0)
where: f
CKIN
is the channel input clock frequency (on given channel CKINy pin) or input data rate in
case of parallel data input.
Bits 28:26 Reserved, must be kept at reset value.
Bits 25:24 RCH[1:0]: Regular channel selection
0: Channel 0 is selected as the regular channel
1: Channel 1 is selected as the regular channel
...
3: Chanel 3 is selected as the regular channel
Writing this bit when RCIP=1 takes effect when the next regular conversion begins. This is
especially useful in continuous mode (when RCONT=1). It also affects regular conversions which
are pending (due to ongoing injected conversion).
Bits 23:22 Reserved, must be kept at reset value.
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