RM0402 Rev 6 375/1163
RM0402 Digital filter for sigma delta modulators (DFSDM)
400
– enabled by JOVRIE bit in DFSDM_FLTxCR2 register
– indicated in JOVRF bit in DFSDM_FLTxISR register
– cleared by writing ‘1’ into CLRJOVRF bit in DFSDM_FLTxICR register
• Data overrun interrupt for regular conversions:
– occurred when regular converted data were not read from DFSDM_FLTxRDATAR
register (by CPU or DMA) and were overwritten by a new regular conversion
– enabled by ROVRIE bit in DFSDM_FLTxCR2 register
– indicated in ROVRF bit in DFSDM_FLTxISR register
– cleared by writing ‘1’ into CLRROVRF bit in DFSDM_FLTxICR register
• Analog watchdog interrupt:
– occurred when converted data (output data or data from analog watchdog filter -
according to AWFSEL bit setting in DFSDM_FLTxCR1 register) crosses
over/under high/low thresholds in DFSDM_FLTxAWHTR / DFSDM_FLTxAWLTR
registers
– enabled by AWDIE bit in DFSDM_FLTxCR2 register (on selected channels
AWDCH[3:0])
– indicated in AWDF bit in DFSDM_FLTxISR register
– separate indication of high or low analog watchdog threshold error by AWHTF[3:0]
and AWLTF[3:0] fields in DFSDM_FLTxAWSR register
– cleared by writing ‘1’ into corresponding CLRAWHTF[3:0] or CLRAWLTF[3:0] bits
in DFSDM_FLTxAWCFR register
• Short-circuit detector interrupt:
– occurred when the number of stable data crosses over thresholds in
DFSDM_CHyAWSCDR register
– enabled by SCDIE bit in DFSDM_FLTxCR2 register (on channel selected by
SCDEN bi tin DFSDM_CHyCFGR1 register)
– indicated in SCDF[3:0] bits in DFSDM_FLTxISR register (which also reports the
channel on which the short-circuit detector event occurred)
– cleared by writing ‘1’ into the corresponding CLRSCDF[3:0] bit in
DFSDM_FLTxICR register
• Channel clock absence interrupt:
– occurred when there is clock absence on CKINy pin (see Clock absence detection
in Section 14.4.4: Serial channel transceivers)
– enabled by CKABIE bit in DFSDM_FLTxCR2 register (on channels selected by
CKABEN bit in DFSDM_CHyCFGR1 register)
– indicated in CKABF[y] bit in DFSDM_FLTxISR register
– cleared by writing ‘1’ into CLRCKABF[y] bit in DFSDM_FLTxICR register
Table 90. DFSDM interrupt requests
Interrupt event Event flag
Event/Interrupt clearing
method
Interrupt enable
control bit
End of injected conversion JEOCF reading DFSDM_FLTxJDATAR JEOCIE
End of regular conversion REOCF reading DFSDM_FLTxRDATAR REOCIE
Injected data overrun JOVRF writing CLRJOVRF = 1 JOVRIE
To Next Page
Loading...
Need help?
General
