ST STM32F412

Flexible static memory controller (FSMC) RM0402
256/1163 RM0402 Rev 6
Mode 1 - SRAM/PSRAM (CRAM)
The next figures show the read and write transactions for the supported modes followed by
the required configuration of FSMC_BCRx, and FSMC_BTRx/FSMC_BWTRx registers.
Figure 33. Mode 1 read access waveforms
Figure 34. Mode 1 write access waveforms
A[25:0]
NOE
ADDSET DATAST
Memory transaction
NEx
D[15:0]
HCLK cycles HCLK cycles
NWE
NBL[1:0]
data driven
by memory
MS34477V1
High
MSv40113V1
A[25:0]
NOE
ADDSET (DATAST + 1)
Memory transaction
NEx
D[15:0]
HCLK cycles
HCLK cycles
NWE
NBL[1:0]
data driven by FSMC
1HCLK