ST STM32F412

Flexible static memory controller (FSMC) RM0402
260/1163 RM0402 Rev 6
Mode 2/B - NOR Flash
Figure 37. Mode 2 and mode B read access waveforms
Table 54. FSMC_BWTRx bitfields (mode A)
Bit number Bit name Value to set
31:30 Reserved 0x0
29:28 ACCMOD 0x0
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST
Duration of the second access phase (DATAST HCLK cycles) for write
accesses.
7:4 ADDHLD Don’t care
3:0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses.
Minimum value for ADDSET is 0.
MS34481V2
A[25:0]
NOE
ADDSET DATAST
Memory transaction
NEx
D[15:0]
HCLK cycles HCLK cycles
NWE
NADV
data driven
by memory
High