ST STM32F412 - Figure 88. Counter Timing Diagram, Internal Clock Divided by 4; Figure 89. Counter Timing Diagram, Internal Clock Divided by N

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Advanced-control timers (TIM1&TIM8) RM0402

422/1163 RM0402 Rev 6

Figure 88. Counter timing diagram, internal clock divided by 4

Figure 89. Counter timing diagram, internal clock divided by N

0000

0001

0000

MS31186V1

CK_PSC

Timerclock = CK_CNT

Counter register

Update event (UEV)

Counter underflow

Update interrupt flag

(UIF)

CNT_EN

001F20

MS31187V1