Digital filter for sigma delta modulators (DFSDM) RM0402
364/1163 RM0402 Rev 6
address is the address of DFSDM_CHyDATINR register. Data are transferred at DMA
transfer speed from memory to DFSDM parallel input.
This DMA transfer is different from DMA used to read DFSDM conversion results. Both
DMA can be used at the same time - first DMA (configured as memory-to-memory
transfer) for input data writings and second DMA (configured as peripheral-to-memory
transfer) for data results reading.
The accesses to DFSDM_CHyDATINR can be either 16-bit or 32-bit wide, allowing to load
respectively one or two samples in one write operation. 32-bit input data register
(DFSDM_CHyDATINR) can be filled with one or two 16-bit data samples, depending on the
data packing operation mode defined in field DATPACK[1:0] of DFSDM_CHyCFGR1
register:
1. Standard mode (DATPACK[1:0]=0):
Only one sample is stored in field INDAT0[15:0] of DFSDM_CHyDATINR register which
is used as input data for channel y. The upper 16 bits (INDAT1[15:0]) are ignored and
write protected. The digital filter must perform one input sampling (from INDAT0[15:0])
to empty data register after it has been filled by CPU/DMA. This mode is used together
with 16-bit CPU/DMA access to DFSDM_CHyDATINR register to load one sample per
write operation.
2. Interleaved mode (DATPACK[1:0]=1):
DFSDM_CHyDATINR register is used as a two sample buffer. The first sample is
stored in INDAT0[15:0] and the second sample is stored in INDAT1[15:0]. The digital
filter must perform two input samplings from channel y to empty DFSDM_CHyDATINR
register. This mode is used together with 32-bit CPU/DMA access to
DFSDM_CHyDATINR register to load two samples per write operation.
3. Dual mode (DATPACK[1:0]=2):
Two samples are written into DFSDM_CHyDATINR register. The data INDAT0[15:0] is
for channel y, the data in INDAT1[15:0] is for channel y+1. The data in INDAT1[15:0] is
automatically copied INDAT0[15:0] of the following (y+1) channel data register
DFSDM_CH[y+1]DATINR). The digital filters must perform two samplings - one from
channel y and one from channel (y+1) - in order to empty DFSDM_CHyDATINR
registers.
Dual mode setting (DATPACK[1:0]=2) is available only on even channel numbers (y =
0, 2). If odd channel (y = 1, 3) is set to Dual mode then both INDAT0[15:0] and
INDAT1[15:0] parts are write protected for this channel. If even channel is set to Dual
mode then the following odd channel must be set into Standard mode
(DATPACK[1:0]=0) for correct cooperation with even channels.
See Figure 73 for DFSDM_CHyDATINR registers data modes and assignments of data
samples to channels.
Figure 73. DFSDM_CHyDATINR registers operation modes and assignment
MSv40123V1
Ch1 (sample 0) Ch0 (sample 0)
Unused Ch1 (sample 0)
Ch3 (sample 0) Ch2 (sample 0)
Unused Ch3 (sample 0)
y = 0
y = 1
y = 2
y = 3
0151631
Ch0 (sample 1) Ch0 (sample 0)
Ch1 (sample 1) Ch1 (sample 0)
Ch2 (sample 1) Ch2 (sample 0)
Ch3 (sample 1) Ch3 (sample 0)
0151631
Unused Ch0 (sample 0)
Unused Ch1 (sample 0)
Unused Ch2 (sample 0)
Unused Ch3 (sample 0)
0151631
Standard mode Interleaved mode Dual mode
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