RM0402 Rev 6 841/1163
RM0402 Serial peripheral interface/ inter-IC sound (SPI/I2S)
862
Figure 294. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0
Figure 295. LSB justified 24-bit frame length with CPOL = 0
• In transmission mode:
If data 0x3478AE have to be transmitted, two write operations to the SPIx_DR register
are required by software or by DMA. The operations are shown below.
Figure 296. Operations required to transmit 0x3478AE
• In reception mode:
If data 0x3478AE are received, two successive read operations from the SPIx_DR
register are required on each RXNE event.
MS30103V1
CK
WS
SD
Transmission
Reception
16- or 32-bit data
MSB
LSB
Channel left
Channel right
MSB
MS30104V1
CK
WS
SD
Transmission
Reception
8-bit data
0 forced
MSB
LSB
Channel left 32-bit
Channel right
24-bit remaining
0xXX34
0x78AE
First write to Data register
conditioned by TXE=1
Second write to Data register
conditioned by TXE=1
Only the 8 LSB of the
half-word are significant.
A field of 0x00 is forced
instead of the 8 MSBs.
MS19596V1
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