ST STM32F412 - Figure 134. Counter Timing Diagram, Internal Clock Divided by 1; Figure 135. Counter Timing Diagram, Internal Clock Divided by 2; Figure 136. Counter Timing Diagram, Internal Clock Divided by 4

RM0402 Rev 6 491/1163
RM0402 General-purpose timers (TIM2 to TIM5)
544
Figure 134. Counter timing diagram, internal clock divided by 1
Figure 135. Counter timing diagram, internal clock divided by 2
Figure 136. Counter timing diagram, internal clock divided by 4
36
34
33
32 31
30 2F
04
03
02 01 00
05
MSv37305V1
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow (cnt_udf)
Update interrupt flag (UIF)
35
MSv37306V1
CK_INT
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag (UIF)
0002 0001 0000 0036 0035 0034 0033
0000 00010001 0000
MSv37307V1
CK_INT
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag (UIF)
CNT_EN