RM0402 Rev 6 265/1163
RM0402 Flexible static memory controller (FSMC)
287
3:2 MTYP 0x02 (NOR Flash memory)
1 MUXEN 0x0
0 MBKEN 0x1
Table 58. FSMC_BCRx bitfields (mode C) (continued)
Bit number Bit name Value to set
Table 59. FSMC_BTRx bitfields (mode C)
Bit number Bit name Value to set
31:30 Reserved 0x0
29:28 ACCMOD 0x2
27:24 DATLAT 0x0
23:20 CLKDIV 0x0
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST
Duration of the second access phase (DATAST HCLK cycles) for
read accesses.
7:4 ADDHLD Don’t care
3:0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses. Minimum value for ADDSET is 0.
Table 60. FSMC_BWTRx bitfields (mode C)
Bit number Bit name Value to set
31:30 Reserved 0x0
29:28 ACCMOD 0x2
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST
Duration of the second access phase (DATAST HCLK cycles) for
write accesses.
7:4 ADDHLD Don’t care
3:0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 0.