ST STM32F412 User Manual

RM0402 Rev 6 141/1163
RM0402 Reset and clock control (RCC) for STM32F412xx
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6.3.12 RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)
Address offset: 0x38
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
6.3.13 RCC APB1 peripheral clock enable register (RCC_APB1ENR)
Address offset: 0x40
Reset value: 0x0000 0400
Access: no wait state, word, half-word and byte access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
QSPI
EN
FSMC
EN
rw rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 QSPIEN: QUADSPI memory controller module clock enable
Set and cleared by software.
0: QUADSPI clock disabled
1: QUADSPI clock enabled
Bit 0 FSMCEN: Flexible memory controller module clock enable
Set and cleared by software.
0: FSMC module clock disabled
1: FSMC module clock enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res.
PWR
EN
Res.
CAN2
EN
CAN1
EN
I2CFMP1
EN
I2C3
EN
I2C2
EN
I2C1
EN
Res. Res.
USART3
EN
USART2
EN
Res.
rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI3
EN
SPI2
EN
Res. Res.
WWDG
EN
RTCAPB Res.
TIM14
EN
TIM13
EN
TIM12
EN
TIM7
EN
TIM6
EN
TIM5
EN
TIM4
EN
TIM3
EN
TIM2
EN
rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:29 Reserved, must be kept at reset value.
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable
Bit 27 Reserved, must be kept at reset value.

ST STM32F412 Specifications

General

Brand	ST
Model	STM32F412
Category	Microcontrollers
Language	English