ST STM32F412 User Manual

RM0402 Rev 6 1043/1163
RM0402 USB on-the-go full-speed (OTG_FS)
1122
29.15.37 OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK)
Address offset: 0x814
Reset value: 0x0000 0000
This register works with each of the OTG_DOEPINTx registers for all endpoints to generate
an interrupt per OUT endpoint. The OUT endpoint interrupt for a specific status in the
OTG_DOEPINTx register can be masked by writing into the corresponding bit in this
register. Status bits are masked by default.
Bit 2 Reserved, must be kept at reset value.
Bit 1 EPDM: Endpoint disabled interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bit 0 XFRCM: Transfer completed interrupt mask
0: Masked interrupt
1: Unmasked interrupt
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res.
NAK
MSK
BERR
M
Res. Res. Res.
OUT
PKT
ERRM
Res. Res.
STS
PHSR
XM
OTEPD
M
STUPM Res. EPDM
XFRC
M
rw rw rw rw rw rw rw rw
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 NAKMSK: NAK interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bit 12 BERRM: Babble error interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 Reserved, must be kept at reset value.
Bit 8 OUTPKTERRM: Out packet error mask
0: Masked interrupt
1: Unmasked interrupt
Bit 7 Reserved, must be kept at reset value.
Bit 6 Reserved, must be kept at reset value.
Bit 5 STSPHSRXM: Status phase received for control write mask
0: Masked interrupt
1: Unmasked interrupt

ST STM32F412 Specifications

General

Brand	ST
Model	STM32F412
Category	Microcontrollers
Language	English