ST STM32F412 User Manual

Reset and clock control (RCC) for STM32F412xx RM0402
144/1163 RM0402 Rev 6
6.3.14 RCC APB2 peripheral clock enable register
(RCC_APB2ENR)
Address offset: 0x44
Reset value: 0x0000 8000
Access: no wait state, word, half-word and byte access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res.
DFSDM1
EN
Res. Res. Res. SPI5EN Res.
TIM11
EN
TIM10
EN
TIM9
EN
rw rw rw rw rw
1514131211109 8765 43210
Res.
SYSCF
G EN
SPI4EN
SPI1
EN
SDIO
EN
Res. Res.
ADC1
EN
Res. Res.
USART6
EN
USART1
EN
Res. Res.
TIM8
EN
TIM1
EN
rw rw rw rw rw rw rw rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 DFSDM1EN: DFSDM1 clock enable
Set and cleared by software
0: DFSDM1 clock disabled
1: DFSDM1 clock enabled
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 SPI5EN:SPI5 clock enable
Set and cleared by software
0: SPI5 clock disabled
1: SPI5 clock enabled
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11EN: TIM11 clock enable
Set and cleared by software.
0: TIM11 clock disabled
1: TIM11 clock enabled
Bit 17 TIM10EN: TIM10 clock enable
Set and cleared by software.
0: TIM10 clock disabled
1: TIM10 clock enabled
Bit 16 TIM9EN: TIM9 clock enable
Set and cleared by software.
0: TIM9 clock disabled
1: TIM9 clock enabled
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGEN: System configuration controller clock enable
Set and cleared by software.
0: System configuration controller clock disabled
1: System configuration controller clock enabled

ST STM32F412 Specifications

General

Brand	ST
Model	STM32F412
Category	Microcontrollers
Language	English