Interrupts and events RM0402
244/1163 RM0402 Rev 6
10.3.6 Pending register (EXTI_PR)
Address offset: 0x14
Reset value: undefined
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. PR22 PR21 Res. Res. PR18 PR17 PR16
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
1514131211109 8 7654321 0
PR15 PR14 PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:21 PR[22:21]: Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line.
This bit is cleared by programming it to ‘1’.
Bits 20:19 Reserved, must be kept at reset value.
Bits 18:0 PR[18:0]: Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line.
This bit is cleared by programming it to ‘1’.