Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit-
774/1163 RM0402 Rev 6
The nearest real number is 0d8 = 0x8 => overflow of the DIV_frac[2:0] => carry must be
added up to the mantissa
DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33
Then, USART_BRR = 0x0330 => USARTDIV = 0d51.000
Table 138. Error calculation for programmed baud rates at f
PCLK
= 8 MHz or f
PCLK
= 12 MHz,
oversampling by 16
(1)
Oversampling by 16 (OVER8=0)
Baud rate f
PCLK
= 8 MHz f
PCLK
= 12 MHz
S.No Desired Actual
Value
programmed
in the baud
rate register
% Error =
(Calculated -
Desired) B.rate /
Desired B.rate
Actual
Value
programmed
in the baud
rate register
% Error
1 1.2 KBps 1.2 KBps 416.6875 0 1.2 KBps 625 0
2 2.4 KBps 2.4 KBps 208.3125 0.01 2.4 KBps 312.5 0
3 9.6 KBps 9.604 KBps 52.0625 0.04 9.6 KBps 78.125 0
4 19.2 KBps 19.185 KBps 26.0625 0.08 19.2 KBps 39.0625 0
5 38.4 KBps 38.462 KBps 13 0.16 38.339 KBps 19.5625 0.16
6 57.6 KBps 57.554 KBps 8.6875 0.08 57.692 KBps 13 0.16
7 115.2 KBps 115.942 KBps 4.3125 0.64 115.385 KBps 6.5 0.16
8 230.4 KBps 228.571 KBps 2.1875 0.79 230.769 KBps 3.25 0.16
9 460.8 KBps 470.588 KBps 1.0625 2.12 461.538 KBps 1.625 0.16
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
Table 139. Error calculation for programmed baud rates at f
PCLK
= 8 MHz or f
PCLK
= 12 MHz,
oversampling by 8
(1)
Oversampling by 8 (OVER8 = 1)
Baud rate f
PCLK
= 8 MHz f
PCLK
= 12 MHz
S.No Desired Actual
Value
programmed
in the baud
rate register
% Error =
(Calculated -
Desired)
B.rate /
Desired
B.rate
Actual
Value
programmed
in the baud
rate register
% Error
1 1.2 KBps 1.2 KBps 833.375 0 1.2 KBps 1250 0
2 2.4 KBps 2.4 KBps 416.625 0.01 2.4 KBps 625 0
3 9.6 KBps 9.604 KBps 104.125 0.04 9.6 KBps 156.25 0
4 19.2 KBps 19.185 KBps 52.125 0.08 19.2 KBps 78.125 0
5 38.4 KBps 38.462 KBps 26 0.16 38.339 KBps 39.125 0.16
To Next Page
Loading...
Need help?
General
