USB on-the-go full-speed (OTG_FS) RM0402
1118/1163 RM0402 Rev 6
request detected bit is set in Global interrupt status register (SRQINT set in
OTG_GINTSTS).
6. The application must service the session request detected interrupt and turn on the
port power bit by writing the port power bit in the host port control and status register.
The PHY indicates port power-on by asserting the VBUS_VALID signal.
7. When the USB is powered, the device connects, completing the SRP process.
B-device session request protocol
The application must set the SRP-capable bit in the core USB configuration register. This
enables the OTG_FS controller to initiate SRP as a B-device. SRP is a means by which the
OTG_FS controller can request a new session from the host.
Figure 356. B-device SRP
1. VBUS_VALID = V
BUS
valid signal from PHY
B_VALID = B-peripheral valid session to PHY
DISCHRG_VBUS = discharge signal to PHY
SESS_END = session end signal to PHY
CHRG_VBUS = charge V
BUS
signal to PHY
DP = Data plus line
DM = Data minus line
The following points refer and describe the signal numeration shown in the Figure 356:
1. To save power, the host suspends and turns off port power when the bus is idle.
The OTG_FS controller sets the early suspend bit in the core interrupt register after 3
ms of bus idleness. Following this, the OTG_FS controller sets the USB suspend bit in
the core interrupt register.
The OTG_FS controller informs the PHY to discharge V
BUS
.
2. The PHY indicates the session’s end to the device. This is the initial condition for SRP.
The OTG_FS controller requires 2 ms of SE0 before initiating SRP.
For a USB 1.1 full-speed serial transceiver, the application must wait until V
BUS
discharges to 0.2 V after BSVLD (in OTG_GOTGCTL) is deasserted. This discharge
ai15682c
VBUS_VALID
B_VALID
DISCHRG_VBUS
SESS_END
DP
DM
CHRG_VBUS
Suspend
Data line pulsing Connect
V
BUS
pulsing
1
6
2
3
4
58
7
Low
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