RM0402 Rev 6 269/1163
RM0402 Flexible static memory controller (FSMC)
287
Figure 45. Muxed write access waveforms
The difference with mode D is the drive of the lower address byte(s) on the data bus.
Table 64. FSMC_BCRx bitfields (Muxed mode)
Bit number Bit name Value to set
31:22 Reserved 0x000
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x0
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN 0x1
5:4 MWID As needed
MSv40112V2
A[25:16]
NOE
Memory transaction
NEx
NWE
NADV
1HCLK
ADDSET
HCLK cycles
(DATAST + 1)
HCLK cycles
ADDHLD
HCLK cycles
AD[15:0] data driven by FSMC
Lower address
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