Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402
842/1163 RM0402 Rev 6
Figure 297. Operations required to receive 0x3478AE
Figure 298. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0
When 16-bit data frame extended to 32-bit channel frame is selected during the I
2
S
configuration phase, Only one access to the SPIx_DR register is required. The 16 remaining
bits are forced by hardware to 0x0000 to extend the data to 32-bit format. In this case it
corresponds to the half-word MSB.
If the data to transmit or the received data are 0x76A3 (0x0000 76A3 extended to 32-bit),
the operation shown in
Figure 299 is required.
Figure 299. Example of 16-bit data frame extended to 32-bit channel frame
In transmission mode, when a TXE event occurs, the application has to write the data to be
transmitted (in this case 0x76A3). The 0x000 field is transmitted first (extension on 32-bit).
The TXE flag is set again as soon as the effective data (0x76A3) is sent on SD.
In reception mode, RXNE is asserted as soon as the significant half-word is received (and
not the 0x0000 field).
In this way, more time is provided between two write or read operations to prevent underrun
or overrun conditions.
0xXX34
0x78AE
First read from Data register
conditioned by RXNE=1
Second read from Data register
conditioned by RXNE=1
Only the 8 LSB of the
half-word are significant.
A field of 0x00 is forced
instead of the 8 MSBs.
MS19597V1
MS30105V1
CK
WS
SD
Transmission
Reception
16-bit data
0 forced
MSB
LSB
Channel left 32-bit
Channel right
16-bit remaining
0x76A3
Only one access to the SPIx-DR register
MS19598V1
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