EasyManuals Logo

ST STM32F412 User Manual

ST STM32F412
1163 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #217 background imageLoading...
Page #217 background image
RM0402 Rev 6 217/1163
RM0402 Direct memory access controller (DMA)
230
9.5 DMA registers
The DMA registers have to be accessed by words (32 bits).
9.5.1 DMA low interrupt status register (DMA_LISR)
Address offset: 0x000
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. TCIF3 HTIF3 TEIF3 DMEIF3 Res. FEIF3 TCIF2 HTIF2 TEIF2 DMEIF2 Res. FEIF2
rr r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. TCIF1 HTIF1 TEIF1 DMEIF1 Res. FEIF1 TCIF0 HTIF0 TEIF0 DMEIF0 Res. FEIF0
rr r r r r r r r r
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 TCIFx: stream x transfer complete interrupt flag (x = 3 to 0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: no transfer complete event on stream x
1: a transfer complete event occurred on stream x
Bits 26, 20, 10, 4 HTIFx: stream x half transfer interrupt flag (x = 3 to 0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: no half transfer event on stream x
1: a half transfer event occurred on stream x
Bits 25, 19, 9, 3 TEIFx: stream x transfer error interrupt flag (x = 3 to 0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: no transfer error on stream x
1: a transfer error occurred on stream x
Bits 24, 18, 8, 2 DMEIFx: stream x direct mode error interrupt flag (x = 3 to 0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No direct mode error on stream x
1: a direct mode error occurred on stream x
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 FEIFx: stream x FIFO error interrupt flag (x = 3 to 0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: no FIFO error event on stream x
1: a FIFO error event occurred on stream x

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ST STM32F412 and is the answer not in the manual?

ST STM32F412 Specifications

General IconGeneral
BrandST
ModelSTM32F412
CategoryMicrocontrollers
LanguageEnglish

Related product manuals