ST STM32F412 User Manual

Independent watchdog (IWDG) RM0402
606/1163 RM0402 Rev 6
A status register is available to indicate that an update of the prescaler or the down-counter
reload value is on going.
20.3.3 Debug mode
When the microcontroller enters debug mode (Cortex
®
-M4 with FPU core halted), the IWDG
counter either continues to work normally or stops, depending on DBG_IWDG_STOP
configuration bit in DBG module. For more details, refer to
Section 30.16.4: Debug MCU
APB1 freeze register (DBGMCU_APB1_FZ).
Figure 204. Independent watchdog block diagram
Note: The watchdog function is implemented in the V
DD
voltage domain that is still functional in
Stop and Standby modes.
IWDG reset
prescaler
IWDG_PR
Prescaler register
IWDG_RLR
Reload register
8-bit
LSI
(40 kHz)
IWDG_KR
Key register
CORE
VDD voltage domain
IWDG_SR
Status register
MS19944V2
12-bit reload value
12-bit downcounter
Table 109. Min/max IWDG timeout period at 32 kHz (LSI)
(1)
1. These timings are given for a 32 kHz clock but the microcontroller internal RC frequency can vary. Refers
to LSI oscillator characteristics table in device datasheet for from max and min values.
Prescaler divider PR[2:0] bits
Min timeout (ms) RL[11:0]=
0x000
Max timeout (ms) RL[11:0]=
0xFFF
/4 0 0.125 512
/8 1 0.25 1024
/16 2 0.5 2048
/32 3 1 4096
/64 4 2 8192
/128 5 4 16384
/256 6 8 32768

ST STM32F412 Specifications

General

Brand	ST
Model	STM32F412
Category	Microcontrollers
Language	English