RM0402 Rev 6 89/1163
RM0402 Power controller (PWR)
108
Backup domain access
After reset, the backup domain (RTC registers, and RTC backup register) is protected
against possible unwanted write accesses. To enable access to the backup domain,
proceed as follows:
• Access to the RTC and RTC backup registers
1. Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR
register (see
Section 6.3.12: RCC AHB3 peripheral clock enable register
(RCC_AHB3ENR))
2. Set the DBP bit in the Section 5.4.1 to enable access to the backup domain
3. Select the RTC clock source: see Section 6.2.8: RTC/AWU clock
4. Enable the RTC clock by programming the RTCEN [15] bit in the Section 6.3.20: RCC
Backup domain control register (RCC_BDCR)
RTC and RTC backup registers
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-
of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable
wakeup flag with interrupt capability. The RTC contains 20 backup data registers (80 bytes)
which are reset when a tamper detection event occurs. For more details refer to
Section 22:
Real-time clock (RTC).
5.1.3 Voltage regulator
An embedded linear voltage regulator supplies all the digital circuitries except for the backup
domain and the Standby circuitry. The regulator output voltage is around 1.2
V.
This voltage regulator requires one or two external capacitors to be connected to one or two
dedicated pins, V
CAP_1
and for some packages V
CAP_2
. Specific pins must be connected
either to V
SS
or V
DD
to activate or deactivate the voltage regulator. These pins depend on
the package.
When activated by software, the voltage regulator is always enabled after Reset. It works in
three different modes depending on the application modes.
• In Run mode, the regulator supplies full power to the 1.2 V domain (core, memories
and digital peripherals). In this mode, the regulator output voltage (around 1.2 V) can
be scaled by software to different voltage values, Scale 1, scale 2, or scale 3, that can
be configured through the VOS[1:0] bits of the PWR_CR register. After reset the VOS
register is set to scale 2. When the PLL is OFF, the voltage regulator is set to scale 3
independently of the VOS register content. The VOS register content is only taken into
account once the PLL is activated and the HSI or HSE is selected as clock source.
The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency.
• In Stop mode, the main regulator or the low-power regulator supplies low power to the
1.2 V domain, thus preserving the content of registers and internal SRAM. The voltage
regulator can be put either in main regulator mode (MR) or in low-power mode (LPR).
The programmed voltage scale remains the same during Stop mode:
Voltage scale 3 is automatically selected when the microcontroller enters Stop mode
(see Section 5.4.1: PWR power control register (PWR_CR)).
• In Standby mode, the regulator is powered down. The content of the registers and
SRAM are lost except for the Standby circuitry and the backup domain.
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