ST STM32F412

To Next Page

To Previous Page

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402

688/1163 RM0402 Rev 6

Figure 230. Transfer bus diagrams for FMPI2C master receiver

MS35979V1

Example FMPI2C master receiver 2 bytes, automatic end mode (STOP)

INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START

EV1: RXNE ISR: rd data1

EV2: RXNE ISR: rd data2

RXNE RXNE

NBYTES

legend:

transmission

reception

SCL stretch

EV1

xx 2

INIT

Example FMPI2C master receiver 2 bytes,software end mode (RESTART)

INIT: program Slave address, program NBYTES = 2, AUTOEND=0, set START

EV1: RXNE ISR: rd data1

EV2: RXNE ISR: read data2

EV3: TC ISR: program Slave address, program NBYTES = N, set START

RXNE RXNE

NBYTES

legend:

transmission

reception

SCL stretch

EV1 EV2

INIT

EV2

AddressS A data1 data2 NA ReS Address

S Address

data1

data2

NA P

Main Page

Table of Contents2
SYSCFG External Interrupt Configuration Register4
Documentation Conventions45
General Information45
List of Abbreviations for Registers45
Glossary46
Availability of Peripherals46
System and Memory Overview47
System Architecture47
Figure 1. System Architecture47
I-Bus48
D-Bus48
S-Bus48
DMA Memory Bus48
DMA Peripheral Bus48
Busmatrix48
AHB/APB Bridges (APB)48
Memory Organization49
Introduction49
Memory Map and Register Boundary Addresses50
Figure 2. Memory Map50
Table 1. Register Boundary Addresses51
Embedded SRAM53
Flash Memory Overview54
Bit Banding54
Boot Configuration55
Table 2. Boot Modes55
Table 3. Embedded Bootloader Interfaces56
Table 4. Memory Mapping Vs. Boot Mode/Physical Remap in Stm32F412Xx56
Embedded Flash Memory Interface58
Introduction58
Main Features58
Figure 3. Flash Memory Interface Connection Inside System Architecture58
Embedded Flash Memory59
Table 5. Flash Module Organization59
Read Interface60
Relation between CPU Clock Frequency and Flash Memory Read Time60
Table 6. Number of Wait States According to CPU Clock (HCLK) Frequency60
Adaptive Real-Time Memory Accelerator (ART Accelerator™)61
Figure 4. Sequential 32-Bit Instruction Execution62
Erase and Program Operations63
Unlocking the Flash Control Register63
Program/Erase Parallelism64
Erase64
Table 7. Program/Erase Parallelism64
Programming65
Interrupts66
Option Bytes66
Description of User Option Bytes66
Table 8. Flash Interrupt Request66
Table 9. Option Byte Organization66
Table 10. Description of the Option Bytes67
Programming User Option Bytes68
Read Protection (RDP)68
Write Protections70
Table 11. Access Versus Read Protection Level70
Figure 5. RDP Levels70
Proprietary Code Readout Protection (PCROP)71
Figure 6. PCROP Levels72
One-Time Programmable Bytes73
Table 12. OTP Area Organization73
Flash Interface Registers74
Flash Access Control Register (FLASH_ACR)74
Flash Key Register (FLASH_KEYR)75
Flash Option Key Register (FLASH_OPTKEYR)75
Flash Status Register (FLASH_SR)76
Flash Control Register (FLASH_CR)77
Flash Option Control Register (FLASH_OPTCR)78
Flash Interface Register Map81
Table 13. Flash Register Map and Reset Values81
CRC Calculation Unit82
CRC Introduction82
CRC Main Features82
CRC Functional Description82
Figure 7. CRC Calculation Unit Block Diagram82
CRC Registers83
Data Register (CRC_DR)83
Independent Data Register (CRC_IDR)84
Control Register (CRC_CR)84
CRC Register Map85
Table 14. CRC Calculation Unit Register Map and Reset Values85
Power Controller (PWR)86
Power Supplies86
Independent A/D Converter Supply and Reference Voltage87
Battery Backup Domain87
Figure 8. Power Supply Overview87
Voltage Regulator89
Power Supply Supervisor90
Power-On Reset (Por)/Power-Down Reset (PDR)90
Brownout Reset (BOR)90
Figure 9. Power-On Reset/Power-Down Reset Waveform90
Programmable Voltage Detector (PVD)91
Figure 10. BOR Thresholds91
Low-Power Modes92
Figure 11. PVD Thresholds92
Slowing down System Clocks94
Peripheral Clock Gating94
Table 15. Low-Power Mode Summary94
Sleep Mode95
Table 16. Sleep-Now Entry and Exit95
Table 17. Sleep-On-Exit Entry and Exit95
Batch Acquisition Mode96
Table 18. BAM-Now Entry and Exit96
Stop Mode97
Table 19. BAM-On-Exit Entry and Exit97
Table 20. Stop Operating Modes98
Table 21. Stop Mode Entry and Exit99
Standby Mode100
Programming the RTC Alternate Functions to Wake up the Device from the Stop and Standby Modes101
Table 22. Standby Mode Entry and Exit101
Power Control Registers104
PWR Power Control Register (PWR_CR)104
PWR Power Control/Status Register (PWR_CSR)106
PWR Register Map108
Table 23. PWR - Register Map and Reset Values108
Reset and Clock Control (RCC) for Stm32F412Xx109
Reset109
System Reset109
Power Reset110
Figure 12. Simplified Diagram of the Reset Circuit110
Backup Domain Reset111
Clocks111
Figure 13. Clock Tree112
HSE Clock113
HSI Clock114
Figure 14. HSE/ LSE Clock Sources114
PLL Configuration115
LSE Clock115
LSI Clock116
System Clock (SYSCLK) Selection116
Clock Security System (CSS)116
RTC/AWU Clock117
Watchdog Clock117
Clock-Out Capability118
Internal/External Clock Measurement Using TIM5/TIM11118
Figure 15. Frequency Measurement with TIM5 in Input Capture Mode119
Figure 16. Frequency Measurement with TIM11 in Input Capture Mode120
RCC Registers121
RCC Clock Control Register (RCC_CR)121
RCC PLL Configuration Register (RCC_PLLCFGR)123
RCC Clock Configuration Register (RCC_CFGR)125
RCC Clock Interrupt Register (RCC_CIR)128
RCC AHB1 Peripheral Reset Register (RCC_AHB1RSTR)130
RCC AHB2 Peripheral Reset Register (RCC_AHB2RSTR)132
RCC AHB3 Peripheral Reset Register (RCC_AHB3RSTR)133
RCC APB1 Peripheral Reset Register for (RCC_APB1RSTR)133
RCC APB2 Peripheral Reset Register (RCC_APB2RSTR)136
RCC AHB1 Peripheral Clock Enable Register (RCC_AHB1ENR)138
RCC AHB2 Peripheral Clock Enable Register (RCC_AHB2ENR)140
RCC AHB3 Peripheral Clock Enable Register (RCC_AHB3ENR)141
RCC APB1 Peripheral Clock Enable Register (RCC_APB1ENR)141
RCC APB2 Peripheral Clock Enable Register (RCC_APB2ENR)144
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB1LPENR)146
RCC AHB2 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB2LPENR)148
RCC AHB3 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB3LPENR)148
RCC APB1 Peripheral Clock Enable in Low Power Mode Register (RCC_APB1LPENR)150
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register (RCC_APB2LPENR)153
RCC Backup Domain Control Register (RCC_BDCR)155
RCC Clock Control & Status Register (RCC_CSR)156
RCC Spread Spectrum Clock Generation Register (RCC_SSCGR)158
RCC PLLI2S Configuration Register (RCC_PLLI2SCFGR)159
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)161
RCC Clocks Gated Enable Register (CKGATENR)162
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR2)163
RCC Register Map164
Table 24. RCC Register Map and Reset Values for Stm32F412Xx164
General-Purpose I/Os (GPIO)167
GPIO Introduction167
GPIO Main Features167
GPIO Functional Description167
Table 25. Port Bit Configuration Table168
Figure 17. Basic Structure of a Five-Volt Tolerant I/O Port Bit168
General-Purpose I/O (GPIO)169
I/O Pin Multiplexer and Mapping170
Table 26. Flexible SWJ-DP Pin Assignment171
Figure 18. Selecting an Alternate Function on Stm32F412Xx172
I/O Port Control Registers173
I/O Port Data Registers173
I/O Data Bitwise Handling173
GPIO Locking Mechanism173
I/O Alternate Function Input/Output174
External Interrupt/Wakeup Lines174
Input Configuration174
Output Configuration175
Figure 19. Input Floating/Pull Up/Pull down Configurations175
Alternate Function Configuration176
Figure 20. Output Configuration176
Figure 21. Alternate Function Configuration176
Analog Configuration177
Using the OSC32_IN/OSC32_OUT Pins as GPIO PC14/PC15177
Port Pins177
Using the OSC_IN/OSC_OUT Pins as GPIO PH0/PH1 Port Pins177
Figure 22. High Impedance-Analog Configuration177
Selection of RTC Additional Functions178
Table 27. RTC Additional Functions178
GPIO Registers179
GPIO Port Mode Register (Gpiox_Moder) (X = a179
GPIO Port Output Type Register (Gpiox_Otyper)179
(X = a179
GPIO Port Output Speed Register (Gpiox_Ospeedr)180
(X = a180
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupdr)180
GPIO Port Input Data Register (Gpiox_Idr) (X = a181
GPIO Port Output Data Register (Gpiox_Odr) (X = a181
GPIO Port Bit Set/Reset Register (Gpiox_Bsrr) (X = a181
GPIO Port Configuration Lock Register (Gpiox_Lckr)182
(X = a182
GPIO Alternate Function Low Register (Gpiox_Afrl) (X = a183
(X = a184
GPIO Register Map184
Table 28. GPIO Register Map and Reset Values184
System Configuration Controller (SYSCFG)187
I/O Compensation Cell187
SYSCFG Registers187
SYSCFG Memory Remap Register (SYSCFG_MEMRMP)187
SYSCFG Peripheral Mode Configuration Register (SYSCFG_PMC)188
SYSCFG External Interrupt Configuration Register 1189
(Syscfg_Exticr1)189
(Syscfg_Exticr2)189
SYSCFG External Interrupt Configuration Register 3190
(Syscfg_Exticr3)190
(Syscfg_Exticr4)191
SYSCFG Configuration Register 2 (SYSCFG_CFGR2)191
Compensation Cell Control Register (SYSCFG_CMPCR)192
SYSCFG Configuration Register (SYSCFG_CFGR)193
SYSCFG Register Map194
Table 29. SYSCFG Register Map and Reset Values194
Direct Memory Access Controller (DMA)195
DMA Introduction195
DMA Main Features195
DMA Functional Description197
DMA Block Diagram197
DMA Overview197
Figure 23. DMA Block Diagram197
DMA Transactions198
Channel Selection198
Figure 24. Channel Selection198
Table 30. DMA1 Request Mapping199
Table 31. DMA2 Request Mapping199
Arbiter200
DMA Streams200
Source, Destination and Transfer Modes200
Table 32. Source and Destination Address200
Figure 25. Peripheral-To-Memory Mode202
Figure 26. Memory-To-Peripheral Mode203
Pointer Incrementation204
Figure 27. Memory-To-Memory Mode204
Circular Mode205
Double-Buffer Mode205
Programmable Data Width, Packing/Unpacking, Endianness206
Table 33. Source and Destination Address Registers in Double-Buffer Mode (DBM = 1)206
Single and Burst Transfers207
Table 34. Packing/Unpacking and Endian Behavior (Bit PINC = MINC = 1)207
Table 35. Restriction on NDT Versus PSIZE and MSIZE207
Fifo208
Figure 28. FIFO Structure209
Table 36. FIFO Threshold Configurations210
DMA Transfer Completion211
DMA Transfer Suspension212
Flow Controller213
Summary of the Possible DMA Configurations214
Stream Configuration Procedure214
Table 37. Possible DMA Configurations214
Error Management215
DMA Interrupts216
Table 38. DMA Interrupt Requests216
DMA Registers217
DMA Low Interrupt Status Register (DMA_LISR)217
DMA High Interrupt Status Register (DMA_HISR)218
DMA Low Interrupt Flag Clear Register (DMA_LIFCR)219
DMA High Interrupt Flag Clear Register (DMA_HIFCR)219
DMA Stream X Configuration Register (Dma_Sxcr)220
DMA Stream X Number of Data Register (Dma_Sxndtr)223
DMA Stream X Peripheral Address Register (Dma_Sxpar)224
DMA Stream X Memory 0 Address Register (Dma_Sxm0Ar)224
DMA Stream X Memory 1 Address Register (Dma_Sxm1Ar)224
DMA Stream X FIFO Control Register (Dma_Sxfcr)225
DMA Register Map227
Table 39. DMA Register Map and Reset Values227
Interrupts and Events231
Nested Vectored Interrupt Controller (NVIC)231
NVIC Features231
Systick Calibration Value Register231
Interrupt and Exception Vectors231
External Interrupt/Event Controller (EXTI)231
Table 40. Vector Table for Stm32F412Xx232
EXTI Main Features235
EXTI Block Diagram236
Wakeup Event Management236
Figure 29. External Interrupt/Event Controller Block Diagram236
Functional Description237
External Interrupt/Event Line Mapping238
Figure 30. External Interrupt/Event GPIO Mapping238
EXTI Registers239
Interrupt Mask Register (EXTI_IMR)239
Event Mask Register (EXTI_EMR)239
Rising Trigger Selection Register (EXTI_RTSR)241
Falling Trigger Selection Register (EXTI_FTSR)242
Software Interrupt Event Register (EXTI_SWIER)243
Pending Register (EXTI_PR)244
EXTI Register Map245
Table 41. External Interrupt/Event Controller Register Map and Reset Values245
Flexible Static Memory Controller (FSMC)246
Introduction246
FSMC Main Features246
FMC Block Diagram247
Figure 31. FSMC Block Diagram247
AHB Interface248
Supported Memories and Transactions248
External Device Address Mapping249
NOR/PSRAM Address Mapping249
Table 42. NOR/PSRAM Bank Selection249
Figure 32. FSMC Memory Banks249
NOR Flash/Psram Controller250
Table 43. NOR/PSRAM External Memory Address250
External Memory Interface Signals251
Table 44. Programmable NOR/PSRAM Access Parameters251
Table 45. Non-Multiplexed I/O nor Flash Memory252
Table 46. 16-Bit Multiplexed I/O nor Flash Memory252
Table 47. Non-Multiplexed I/Os PSRAM/SRAM252
Supported Memories and Transactions253
Table 48. 16-Bit Multiplexed I/O PSRAM253
Table 49. nor Flash/Psram: Example of Supported Memories254
And Transactions254
General Timing Rules255
NOR Flash/Psram Controller Asynchronous Transactions255
Figure 33. Mode 1 Read Access Waveforms256
Figure 34. Mode 1 Write Access Waveforms256
Table 50. Fsmc_Bcrx Bitfields (Mode 1)257
Table 51. Fsmc_Btrx Bitfields (Mode 1)257
Figure 35. Mode a Read Access Waveforms258
Figure 36. Mode a Write Access Waveforms258
Table 52. Fsmc_Bcrx Bitfields (Mode A)259
Table 53. Fsmc_Btrx Bitfields (Mode A)259
Table 54. Fsmc_Bwtrx Bitfields (Mode A)260
Figure 37. Mode 2 and Mode B Read Access Waveforms260
Figure 38. Mode 2 Write Access Waveforms261
Figure 39. Mode B Write Access Waveforms261
Table 55. Fsmc_Bcrx Bitfields (Mode 2/B)262
Table 56. Fsmc_Btrx Bitfields (Mode 2/B)262
Table 57. Fsmc_Bwtrx Bitfields (Mode 2/B)263
Figure 40. Mode C Read Access Waveforms263
Table 58. Fsmc_Bcrx Bitfields (Mode C)264
Figure 41. Mode C Write Access Waveforms264
Table 59. Fsmc_Btrx Bitfields (Mode C)265
Table 60. Fsmc_Bwtrx Bitfields (Mode C)265
Figure 42. Mode D Read Access Waveforms266
Figure 43. Mode D Write Access Waveforms266
Table 61. Fsmc_Bcrx Bitfields (Mode D)267
Table 62. Fsmc_Btrx Bitfields (Mode D)267
Table 63. Fsmc_Bwtrx Bitfields (Mode D)268
Figure 44. Muxed Read Access Waveforms268
Table 64. Fsmc_Bcrx Bitfields (Muxed Mode)269
Figure 45. Muxed Write Access Waveforms269
Table 65. Fsmc_Btrx Bitfields (Muxed Mode)270
Figure 46. Asynchronous Wait During a Read Access Waveforms271
Synchronous Transactions272
Figure 47. Asynchronous Wait During a Write Access Waveforms272
Figure 48. Wait Configuration Waveforms274
Table 66. Fsmc_Bcrx Bitfields (Synchronous Multiplexed Read Mode)275
Figure 49. Synchronous Multiplexed Read Mode Waveforms - NOR, PSRAM (CRAM)275
Table 67. Fsmc_Btrx Bitfields (Synchronous Multiplexed Read Mode)276
Figure 50. Synchronous Multiplexed Write Mode Waveforms - PSRAM (CRAM)277
Table 68. Fsmc_Bcrx Bitfields (Synchronous Multiplexed Write Mode)278
Table 69. Fsmc_Btrx Bitfields (Synchronous Multiplexed Write Mode)278
NOR/PSRAM Controller Registers279
FSMC Register Map286
Table 70. FSMC Register Map and Reset Values286
Quad-SPI Interface (QUADSPI)288
Introduction288
QUADSPI Main Features288
QUADSPI Functional Description288
QUADSPI Block Diagram288
Figure 51. QUADSPI Block Diagram When Dual-Flash Mode Is Disabled288
QUADSPI Pins289
Table 71. QUADSPI Pins289
Figure 52. QUADSPI Block Diagram When Dual-Flash Mode Is Enabled289
QUADSPI Command Sequence290
Figure 53. an Example of a Read Command in Quad Mode290
QUADSPI Signal Interface Protocol Modes292
Figure 54. an Example of a DDR Command in Quad Mode293
QUADSPI Indirect Mode294
QUADSPI Status Flag Polling Mode296
QUADSPI Memory-Mapped Mode296
QUADSPI Flash Memory Configuration297
QUADSPI Delayed Data Sampling297
QUADSPI Configuration297
QUADSPI Usage298
Sending the Instruction Only Once300
QUADSPI Error Management300
QUADSPI Busy Bit and Abort Functionality300
Ncs Behavior301
Figure 55. Ncs When CKMODE = 0 (T = CLK Period)301
Figure 56. Ncs When CKMODE = 1 in SDR Mode (T = CLK Period)301
QUADSPI Interrupts302
Figure 57. Ncs When CKMODE = 1 in DDR Mode (T = CLK Period)302
Figure 58. Ncs When CKMODE = 1 with an Abort (T = CLK Period)302
Table 72. QUADSPI Interrupt Requests303
QUADSPI Registers304
QUADSPI Control Register (QUADSPI_CR)304
QUADSPI Device Configuration Register (QUADSPI_DCR)307
QUADSPI Status Register (QUADSPI_SR)308
QUADSPI Flag Clear Register (QUADSPI_FCR)309
QUADSPI Data Length Register (QUADSPI_DLR)309
QUADSPI Communication Configuration Register (QUADSPI_CCR)310
QUADSPI Address Register (QUADSPI_AR)312
QUADSPI Alternate Bytes Registers (QUADSPI_ABR)313
QUADSPI Data Register (QUADSPI_DR)313
QUADSPI Polling Status Mask Register (QUADSPI_PSMKR)314
QUADSPI Polling Status Match Register (QUADSPI_PSMAR)314
QUADSPI Polling Interval Register (QUADSPI_PIR)315
QUADSPI Low-Power Timeout Register (QUADSPI_LPTR)315
QUADSPI Register Map316
Table 73. QUADSPI Register Map and Reset Values316
Analog-To-Digital Converter (ADC)317
ADC Introduction317
ADC Main Features317
ADC Functional Description317
Figure 59. Single ADC Block Diagram318
ADC On-Off Control319
ADC Clock319
Channel Selection319
Table 74. ADC Pins319
Single Conversion Mode320
Continuous Conversion Mode320
Timing Diagram321
Analog Watchdog321
Figure 60. Timing Diagram321
Scan Mode322
Table 75. Analog Watchdog Channel Selection322
Figure 61. Analog Watchdog's Guarded Area322
Injected Channel Management323
Figure 62. Injected Conversion Latency323
Discontinuous Mode324
Data Alignment325
Figure 63. Right Alignment of 12-Bit Data325
Figure 64. Left Alignment of 12-Bit Data325
Figure 65. Left Alignment of 6-Bit Data325
Channel-Wise Programmable Sampling Time326
Conversion on External Trigger and Trigger Polarity326
Table 76. Configuring the Trigger Polarity326
Table 77. External Trigger for Regular Channels327
Fast Conversion Mode328
Table 78. External Trigger for Injected Channels328
Data Management329
Using the DMA329
Managing a Sequence of Conversions Without Using the DMA329
Conversions Without DMA and Without Overrun Detection330
Temperature Sensor330
Figure 66. Temperature Sensor and VREFINT Channel Block Diagram330
Battery Charge Monitoring331
ADC Interrupts332
Table 79. ADC Interrupts332
ADC Registers333
ADC Status Register (ADC_SR)333
ADC Control Register 1 (ADC_CR1)334
ADC Control Register 2 (ADC_CR2)336
ADC Sample Time Register 1 (ADC_SMPR1)338
ADC Sample Time Register 2 (ADC_SMPR2)339
ADC Injected Channel Data Offset Register X (Adc_Jofrx) (X=1339
ADC Watchdog Higher Threshold Register (ADC_HTR)339
ADC Watchdog Lower Threshold Register (ADC_LTR)340
ADC Regular Sequence Register 1 (ADC_SQR1)340
ADC Regular Sequence Register 2 (ADC_SQR2)341
ADC Regular Sequence Register 3 (ADC_SQR3)342
ADC Injected Sequence Register (ADC_JSQR)343
ADC Injected Data Register X (Adc_Jdrx) (X= 1343
ADC Regular Data Register (ADC_DR)344
ADC Common Status Register (ADC_CSR)344
ADC Common Control Register (ADC_CCR)345
ADC Register Map346
Table 80. ADC Global Register Map346
Table 81. ADC Register Map and Reset Values346
Table 82. ADC Register Map and Reset Values (Common ADC Registers)347
Digital Filter for Sigma Delta Modulators (DFSDM)348
Introduction348
DFSDM Main Features349
DFSDM Implementation350
Table 83. DFSDM1 Implementation350
DFSDM Functional Description351
DFSDM Block Diagram351
Figure 67. Single DFSDM Block Diagram351
DFSDM Pins and Internal Signals352
Table 84. DFSDM External Pins352
Table 85. DFSDM Internal Signals352
Table 86. DFSDM Triggers Connection352
DFSDM Reset and Clocks353
Table 87. DFSDM Break Connection353
Serial Channel Transceivers354
Figure 68. Input Channel Pins Redirection355
Figure 69. Channel Transceiver Timing Diagrams357
Figure 70. Clock Absence Timing Diagram for SPI358
Figure 71. Clock Absence Timing Diagram for Manchester Coding359
Figure 72. First Conversion for Manchester Coding (Manchester Synchronization)361
Configuring the Input Serial Interface363
Parallel Data Inputs363
Figure 73. Dfsdm_Chydatinr Registers Operation Modes and Assignment364
Channel Selection365
Digital Filter Configuration365
Figure 74. Example: Sinc3 Filter Response366
Integrator Unit367
Analog Watchdog367
Table 88. Filter Maximum Output Resolution (Peak Data Values from Filter Output)367
Table 89. Integrator Maximum Output Resolution367
Short-Circuit Detector370
Extreme Detector370
Data Unit Block371
Signed Data Format372
Launching Conversions372
Continuous and Fast Continuous Modes373
Request Precedence373
Power Optimization in Run Mode374
DFSDM Interrupts374
Table 90. DFSDM Interrupt Requests375
DFSDM DMA Transfer376
DFSDM Channel y Registers (Y=0376
DFSDM Channel y Configuration Register (Dfsdm_Chycfgr1)376
DFSDM Channel y Configuration Register (Dfsdm_Chycfgr2)379
DFSDM Channel y Analog Watchdog and Short-Circuit Detector Register (Dfsdm_Chyawscdr)379
DFSDM Channel y Watchdog Filter Data Register (Dfsdm_Chywdatr)380
DFSDM Channel y Data Input Register (Dfsdm_Chydatinr)381
DFSDM Filter X Module Registers (X=0382
DFSDM Filter X Control Register 1 (Dfsdm_Fltxcr1)382
DFSDM Filter X Control Register 2 (Dfsdm_Fltxcr2)384
DFSDM Filter X Interrupt and Status Register (Dfsdm_Fltxisr)386
DFSDM Filter X Interrupt Flag Clear Register (Dfsdm_Fltxicr)387
DFSDM Filter X Injected Channel Group Selection Register (Dfsdm_Fltxjchgr)388
DFSDM Filter X Control Register (Dfsdm_Fltxfcr)389
DFSDM Filter X Data Register for Injected Group (Dfsdm_Fltxjdatar)390
DFSDM Filter X Data Register for the Regular Channel (Dfsdm_Fltxrdatar)391
DFSDM Filter X Analog Watchdog High Threshold Register (Dfsdm_Fltxawhtr)391
DFSDM Filter X Analog Watchdog Low Threshold Register392
(Dfsdm_Fltxawltr)392
DFSDM Filter X Analog Watchdog Status Register393
(Dfsdm_Fltxawsr)393
DFSDM Filter X Analog Watchdog Clear Flag Register393
(Dfsdm_Fltxawcfr)393
DFSDM Filter X Extremes Detector Maximum Register394
(Dfsdm_Fltxexmax)394
DFSDM Filter X Extremes Detector Minimum Register394
(Dfsdm_Fltxexmin)394
DFSDM Filter X Conversion Timer Register (Dfsdm_Fltxcnvtimr)395
DFSDM Register Map396
Table 91. DFSDM Register Map and Reset Values396
True Random Number Generator (RNG)401
Introduction401
RNG Main Features401
RNG Functional Description402
RNG Block Diagram402
RNG Internal Signals402
Table 92. RNG Internal Input/Output Signals402
Figure 75. RNG Block Diagram402
Random Number Generation403
Figure 76. Entropy Source Model403
RNG Initialization405
RNG Operation405
RNG Clocking406
Error Management406
RNG Low-Power Usage407
RNG Interrupts407
RNG Processing Time407
Table 93. RNG Interrupt Requests407
RNG Entropy Source Validation408
Introduction408
Validation Conditions408
Data Collection408
RNG Registers409
RNG Control Register (RNG_CR)409
RNG Status Register (RNG_SR)410
RNG Data Register (RNG_DR)411
RNG Register Map412
Table 94. RNG Register Map and Reset Map412
Advanced-Control Timers (TIM1&TIM8)413
TIM1&TIM8 Introduction413
TIM1&TIM8 Main Features413
Figure 77. Advanced-Control Timer Block Diagram414
TIM1&TIM8 Functional Description415
Time-Base Unit415
Figure 78. Counter Timing Diagram with Prescaler Division Change from 1 to 2416
Figure 79. Counter Timing Diagram with Prescaler Division Change from 1 to 4416
Counter Modes417
Figure 80. Counter Timing Diagram, Internal Clock Divided by 1417
Figure 81. Counter Timing Diagram, Internal Clock Divided by 2418
Figure 82. Counter Timing Diagram, Internal Clock Divided by 4418
Figure 83. Counter Timing Diagram, Internal Clock Divided by N418
Figure 84. Counter Timing Diagram, Update Event When ARPE=0419
Figure 85. Counter Timing Diagram, Update Event When ARPE=1419
Figure 86. Counter Timing Diagram, Internal Clock Divided by 1421
Figure 87. Counter Timing Diagram, Internal Clock Divided by 2421
Figure 88. Counter Timing Diagram, Internal Clock Divided by 4422
Figure 89. Counter Timing Diagram, Internal Clock Divided by N422
Figure 90. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used423
Figure 91. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6424
Figure 92. Counter Timing Diagram, Internal Clock Divided by 2424
Figure 93. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36425
Figure 94. Counter Timing Diagram, Internal Clock Divided by N425
Repetition Counter426
Figure 95. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)426
Figure 96. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)426
Figure 97. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings427
Clock Selection428
Figure 98. Control Circuit in Normal Mode, Internal Clock Divided by 1428
Figure 99. TI2 External Clock Connection Example429
Figure 100. Control Circuit in External Clock Mode 1430
Figure 101. External Trigger Input Block430
Capture/Compare Channels431
Figure 102. Control Circuit in External Clock Mode 2431
Figure 103. Capture/Compare Channel (Example: Channel 1 Input Stage)432
Figure 104. Capture/Compare Channel 1 Main Circuit432
Figure 105. Output Stage of Capture/Compare Channel (Channels 1 to 3)433
Figure 106. Output Stage of Capture/Compare Channel (Channel 4)433
Input Capture Mode434
PWM Input Mode435
Forced Output Mode435
Figure 107. PWM Input Mode Timing435
Output Compare Mode436
PWM Mode437
Figure 108. Output Compare Mode, Toggle on OC1437
Figure 109. Edge-Aligned PWM Waveforms (ARR=8)438
Figure 110. Center-Aligned PWM Waveforms (ARR=8)439
Complementary Outputs and Dead-Time Insertion440
Figure 111. Complementary Output with Dead-Time Insertion441
Figure 112. Dead-Time Waveforms with Delay Greater than the Negative Pulse441
Figure 113. Dead-Time Waveforms with Delay Greater than the Positive Pulse441
Using the Break Function442
Figure 114. Output Behavior in Response to a Break444
Clearing the Ocxref Signal on an External Event445
Figure 115. Clearing Timx Ocxref445
6-Step PWM Generation446
Figure 116. 6-Step Generation, COM Example (OSSR=1)446
One-Pulse Mode447
Figure 117. Example of One Pulse Mode447
Encoder Interface Mode448
Table 95. Counting Direction Versus Encoder Signals449
Figure 118. Example of Counter Operation in Encoder Interface Mode450
Figure 119. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted450
Timer Input XOR Function451
Interfacing with Hall Sensors451
Figure 120. Example of Hall Sensor Interface452
Timx and External Trigger Synchronization453
Figure 121. Control Circuit in Reset Mode453
Figure 122. Control Circuit in Gated Mode454
Figure 123. Control Circuit in Trigger Mode455
Timer Synchronization456
Debug Mode456
Figure 124. Control Circuit in External Clock Mode 2 + Trigger Mode456
TIM1&TIM8 Registers457
TIM1&TIM8 Control Register 1 (Timx_Cr1)457
TIM1&TIM8 Control Register 2 (Timx_Cr2)458
TIM1&TIM8 Slave Mode Control Register (Timx_Smcr)460
TIM1&TIM8 Dma/Interrupt Enable Register (Timx_Dier)462
Table 96. Timx Internal Trigger Connection462
TIM1&TIM8 Status Register (Timx_Sr)464
TIM1&TIM8 Event Generation Register (Timx_Egr)465
TIM1&TIM8 Capture/Compare Mode Register 1 (Timx_Ccmr1)467
TIM1&TIM8 Capture/Compare Mode Register 2 (Timx_Ccmr2)470
TIM1&TIM8 Capture/Compare Enable Register (Timx_Ccer)471
Table 97. Output Control Bits for Complementary Ocx and Ocxn Channels474
TIM1&TIM8 Counter (Timx_Cnt)475
TIM1&TIM8 Prescaler (Timx_Psc)475
TIM1&TIM8 Auto-Reload Register (Timx_Arr)475
TIM1&TIM8 Repetition Counter Register (Timx_Rcr)476
TIM1&TIM8 Capture/Compare Register 1 (Timx_Ccr1)476
TIM1&TIM8 Capture/Compare Register 2 (Timx_Ccr2)477
TIM1&TIM8 Capture/Compare Register 3 (Timx_Ccr3)477
TIM1&TIM8 Capture/Compare Register 4 (Timx_Ccr4)478
TIM1&TIM8 Break and Dead-Time Register (Timx_Bdtr)478
TIM1&TIM8 DMA Control Register (Timx_Dcr)480
TIM1&TIM8 DMA Address for Full Transfer (Timx_Dmar)481
TIM1&TIM8 Register Map482
Table 98. TIM1&TIM8 Register Map and Reset Values482
General-Purpose Timers (TIM2 to TIM5)484
TIM2 to TIM5 Introduction484
TIM2 to TIM5 Main Features484
TIM2 to TIM5 Functional Description485
Time-Base Unit485
Figure 125. General-Purpose Timer Block Diagram485
Figure 126. Counter Timing Diagram with Prescaler Division Change from 1 to 2486
Counter Modes487
Figure 127. Counter Timing Diagram with Prescaler Division Change from 1 to 4487
Figure 128. Counter Timing Diagram, Internal Clock Divided by 1488
Figure 129. Counter Timing Diagram, Internal Clock Divided by 2488
Figure 130. Counter Timing Diagram, Internal Clock Divided by 4488
Figure 131. Counter Timing Diagram, Internal Clock Divided by N489
Figure 132. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)489
Figure 133. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)490
Figure 134. Counter Timing Diagram, Internal Clock Divided by 1491
Figure 135. Counter Timing Diagram, Internal Clock Divided by 2491
Figure 136. Counter Timing Diagram, Internal Clock Divided by 4491
Figure 137. Counter Timing Diagram, Internal Clock Divided by N492
Figure 138. Counter Timing Diagram, Update Event492
Figure 139. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6493
Figure 140. Counter Timing Diagram, Internal Clock Divided by 2494
Figure 141. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36494
Figure 142. Counter Timing Diagram, Internal Clock Divided by N494
Figure 143. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)495
Figure 144. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)495
Clock Selection496
Figure 145. Control Circuit in Normal Mode, Internal Clock Divided by 1496
Figure 146. TI2 External Clock Connection Example497
Figure 147. Control Circuit in External Clock Mode 1498
Figure 148. External Trigger Input Block498
Capture/Compare Channels499
Figure 149. Control Circuit in External Clock Mode 2499
Figure 150. Capture/Compare Channel (Example: Channel 1 Input Stage)500
Figure 151. Capture/Compare Channel 1 Main Circuit500
Input Capture Mode501
Figure 152. Output Stage of Capture/Compare Channel (Channel 1)501
PWM Input Mode502
Forced Output Mode503
Figure 153. PWM Input Mode Timing503
Output Compare Mode504
PWM Mode505
Figure 154. Output Compare Mode, Toggle on OC1505
Figure 155. Edge-Aligned PWM Waveforms (ARR=8)506
Figure 156. Center-Aligned PWM Waveforms (ARR=8)507
One-Pulse Mode508
Figure 157. Example of One-Pulse Mode508
Clearing the Ocxref Signal on an External Event509
Encoder Interface Mode510
Figure 158. Clearing Timx Ocxref510
Table 99. Counting Direction Versus Encoder Signals511
Figure 159. Example of Counter Operation in Encoder Interface Mode512
Figure 160. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted512
Timer Input XOR Function513
Timers and External Trigger Synchronization513
Figure 161. Control Circuit in Reset Mode513
Figure 162. Control Circuit in Gated Mode514
Figure 163. Control Circuit in Trigger Mode515
Timer Synchronization516
Figure 164. Control Circuit in External Clock Mode 2 + Trigger Mode516
Figure 165. Master/Slave Timer Example516
Figure 166. Gating Timer 2 with OC1REF of Timer 1517
Figure 167. Gating Timer 2 with Enable of Timer 1518
Figure 168. Triggering Timer 2 with Update of Timer 1519
Figure 169. Triggering Timer 2 with Enable of Timer 1520
Debug Mode521
Figure 170. Triggering Timer 1 and 2 with Timer 1 TI1 Input521
TIM2 to TIM5 Registers522
Timx Control Register 1 (Timx_Cr1)522
Timx Control Register 2 (Timx_Cr2)524
Timx Slave Mode Control Register (Timx_Smcr)525
Table 100. Timx Internal Trigger Connections526
Timx Dma/Interrupt Enable Register (Timx_Dier)527
Timx Status Register (Timx_Sr)528
Timx Event Generation Register (Timx_Egr)530
Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)531
Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)534
Timx Capture/Compare Enable Register (Timx_Ccer)535
Table 101. Output Control Bit for Standard Ocx Channels536
Timx Counter (Timx_Cnt)537
Timx Prescaler (Timx_Psc)537
Timx Auto-Reload Register (Timx_Arr)537
Timx Capture/Compare Register 1 (Timx_Ccr1)538
Timx Capture/Compare Register 2 (Timx_Ccr2)538
Timx Capture/Compare Register 3 (Timx_Ccr3)539
Timx Capture/Compare Register 4 (Timx_Ccr4)539
Timx DMA Control Register (Timx_Dcr)540
Timx DMA Address for Full Transfer (Timx_Dmar)540
TIM2 Option Register (TIM2_OR)541
TIM5 Option Register (TIM5_OR)542
Timx Register Map543
Table 102. TIM2 to TIM5 Register Map and Reset Values543
General-Purpose Timers (TIM9 to TIM14)545
TIM9 to TIM14 Introduction545
TIM9 to TIM14 Main Features545
TIM9/TIM12 Main Features545
TIM10/TIM11 and TIM13/TIM14 Main Features546
Figure 171. General-Purpose Timer Block Diagram (TIM9 and TIM12)546
Figure 172. General-Purpose Timer Block Diagram (TIM10/11/13/14)547
TIM9 to TIM14 Functional Description548
Time-Base Unit548
Figure 173. Counter Timing Diagram with Prescaler Division Change from 1 to 2549
Figure 174. Counter Timing Diagram with Prescaler Division Change from 1 to 4549
Counter Modes550
Figure 175. Counter Timing Diagram, Internal Clock Divided by 1550
Figure 176. Counter Timing Diagram, Internal Clock Divided by 2551
Figure 177. Counter Timing Diagram, Internal Clock Divided by 4551
Figure 178. Counter Timing Diagram, Internal Clock Divided by N551
Figure 179. Counter Timing Diagram, Update Event When ARPE=0552
Figure 180. Counter Timing Diagram, Update Event When ARPE=1552
Clock Selection553
Figure 181. Control Circuit in Normal Mode, Internal Clock Divided by 1553
Figure 182. TI2 External Clock Connection Example554
Figure 183. Control Circuit in External Clock Mode 1554
Capture/Compare Channels555
Figure 184. Capture/Compare Channel (Example: Channel 1 Input Stage)555
Input Capture Mode556
Figure 185. Capture/Compare Channel 1 Main Circuit556
Figure 186. Output Stage of Capture/Compare Channel (Channel 1)556
PWM Input Mode (Only for TIM9/12)557
Forced Output Mode558
Figure 187. PWM Input Mode Timing558
Output Compare Mode559
PWM Mode560
Figure 188. Output Compare Mode, Toggle on OC1560
One-Pulse Mode561
Figure 189. Edge-Aligned PWM Waveforms (ARR=8)561
Figure 190. Example of One Pulse Mode562
TIM9/12 External Trigger Synchronization563
Figure 191. Control Circuit in Reset Mode564
Figure 192. Control Circuit in Gated Mode565
Figure 193. Control Circuit in Trigger Mode565
Timer Synchronization (TIM9/12)566
Debug Mode566
TIM9 and TIM12 Registers566
TIM9/12 Control Register 1 (Timx_Cr1)566
TIM9/12 Slave Mode Control Register (Timx_Smcr)568
TIM9/12 Interrupt Enable Register (Timx_Dier)569
Table 103. Timx Internal Trigger Connections569
TIM9/12 Status Register (Timx_Sr)570
TIM9/12 Event Generation Register (Timx_Egr)572
TIM9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)572
TIM9/12 Capture/Compare Enable Register (Timx_Ccer)576
TIM9/12 Counter (Timx_Cnt)577
TIM9/12 Prescaler (Timx_Psc)577
TIM9/12 Auto-Reload Register (Timx_Arr)577
Table 104. Output Control Bit for Standard Ocx Channels577
TIM9/12 Capture/Compare Register 1 (Timx_Ccr1)578
TIM9/12 Capture/Compare Register 2 (Timx_Ccr2)578
TIM9/12 Register Map579
Table 105. TIM9/12 Register Map and Reset Values579
TIM10/11/13/14 Registers581
TIM10/11/13/14 Control Register 1 (Timx_Cr1)581
TIM10/11/13/14 Interrupt Enable Register (Timx_Dier)582
TIM10/11/13/14 Status Register (Timx_Sr)582
TIM10/11/13/14 Event Generation Register (Timx_Egr)583
TIM10/11/13/14 Capture/Compare Mode Register 1584
(Timx_Ccmr1)584
TIM10/11/13/14 Capture/Compare Enable Register587
(Timx_Ccer)587
Table 106. Output Control Bit for Standard Ocx Channels587
TIM10/11/13/14 Counter (Timx_Cnt)588
TIM10/11/13/14 Prescaler (Timx_Psc)588
TIM10/11/13/14 Auto-Reload Register (Timx_Arr)588
TIM10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)589
TIM11 Option Register 1 (TIM11_OR)589
TIM10/11/13/14 Register Map590
Table 107. TIM10/11/13/14 Register Map and Reset Values590
Basic Timers (TIM6/7)592
Introduction592
TIM6/7 Main Features592
Figure 194. Basic Timer Block Diagram592
TIM6/7 Functional Description593
Time-Base Unit593
Figure 195. Counter Timing Diagram with Prescaler Division Change from 1 to 2594
Figure 196. Counter Timing Diagram with Prescaler Division Change from 1 to 4594
Counting Mode595
Figure 197. Counter Timing Diagram, Internal Clock Divided by 1595
Figure 198. Counter Timing Diagram, Internal Clock Divided by 2596
Figure 199. Counter Timing Diagram, Internal Clock Divided by 4596
Figure 200. Counter Timing Diagram, Internal Clock Divided by N597
Clock Source598
Debug Mode599
Figure 203. Control Circuit in Normal Mode, Internal Clock Divided by 1599
TIM6/7 Registers600
TIM6/7 Control Register 1 (Timx_Cr1)600
TIM6/7 Control Register 2 (Timx_Cr2)601
TIM6/7 Dma/Interrupt Enable Register (Timx_Dier)601
TIM6/7 Status Register (Timx_Sr)602
TIM6/7 Event Generation Register (Timx_Egr)602
TIM6/7 Counter (Timx_Cnt)602
TIM6/7 Prescaler (Timx_Psc)603
TIM6/7 Auto-Reload Register (Timx_Arr)603
TIM6/7 Register Map604
Table 108. TIM6/7 Register Map and Reset Values604
Independent Watchdog (IWDG)605
IWDG Introduction605
IWDG Main Features605
IWDG Functional Description605
Hardware Watchdog605
Register Access Protection605
Debug Mode606
Table 109. Min/Max IWDG Timeout Period at 32 Khz (LSI)606
Figure 204. Independent Watchdog Block Diagram606
IWDG Registers607
Key Register (IWDG_KR)607
Prescaler Register (IWDG_PR)608
Reload Register (IWDG_RLR)609
Status Register (IWDG_SR)609
IWDG Register Map610
Table 110. IWDG Register Map and Reset Values610
Window Watchdog (WWDG)611
WWDG Introduction611
WWDG Main Features611
WWDG Functional Description611
Figure 205. Watchdog Block Diagram612
How to Program the Watchdog Timeout613
Figure 206. Window Watchdog Timing Diagram613
Debug Mode614
WWDG Registers615
Control Register (WWDG_CR)615
Configuration Register (WWDG_CFR)616
Status Register (WWDG_SR)616
WWDG Register Map617
Table 111. WWDG Register Map and Reset Values617
Real-Time Clock (RTC)618
Introduction618
RTC Main Features618
RTC Functional Description620
Clock and Prescalers620
Real-Time Clock and Calendar620
Figure 207. RTC Block Diagram620
Programmable Alarms621
Periodic Auto-Wakeup621
RTC Initialization and Configuration622
Reading the Calendar624
Resetting the RTC625
RTC Synchronization625
RTC Reference Clock Detection626
RTC Coarse Digital Calibration626
RTC Smooth Digital Calibration627
Timestamp Function629
Tamper Detection630
Calibration Clock Output631
Alarm Output632
RTC and Low Power Modes632
Table 112. Effect of Low Power Modes on RTC632
RTC Interrupts633
Table 113. Interrupt Control Bits633
RTC Registers634
RTC Time Register (RTC_TR)634
RTC Date Register (RTC_DR)635
RTC Control Register (RTC_CR)636
RTC Initialization and Status Register (RTC_ISR)638
RTC Prescaler Register (RTC_PRER)640
RTC Wakeup Timer Register (RTC_WUTR)641
RTC Calibration Register (RTC_CALIBR)641
RTC Alarm a Register (RTC_ALRMAR)643
RTC Alarm B Register (RTC_ALRMBR)644
RTC Write Protection Register (RTC_WPR)645
RTC Sub Second Register (RTC_SSR)645
RTC Shift Control Register (RTC_SHIFTR)646
RTC Time Stamp Time Register (RTC_TSTR)647
RTC Time Stamp Date Register (RTC_TSDR)647
RTC Timestamp Sub Second Register (RTC_TSSSR)648
RTC Calibration Register (RTC_CALR)648
RTC Tamper and Alternate Function Configuration Register649
(Rtc_Tafcr)649
RTC Alarm a Sub Second Register (RTC_ALRMASSR)651
RTC Alarm B Sub Second Register (RTC_ALRMBSSR)652
RTC Backup Registers (Rtc_Bkpxr)653
RTC Register Map653
Table 114. RTC Register Map and Reset Values653
Fast-Mode Plus Inter-Integrated Circuit (FMPI2C) Interface656
Introduction656
FMPI2C Main Features656
FMPI2C Implementation657
FMPI2C Functional Description657
Table 115. Stm32F412Xx FMPI2C Implementation657
FMPI2C Block Diagram658
Figure 208. FMPI2C Block Diagram658
FMPI2C Pins and Internal Signals659
FMPI2C Clock Requirements659
Table 116. FMPI2C Input/Output Pins659
Table 117. FMPI2C Internal Input/Output Signals659
Mode Selection660
FMPI2C Initialization660
Figure 209. I2C Bus Protocol660
Table 118. Comparison of Analog Vs. Digital Filters661
Figure 210. Setup and Hold Timings662
Table 119. I2C-Smbus Specification Data Setup and Hold Times663
Software Reset665
Figure 211. FMPI2C Initialization Flowchart665
Data Transfer666
Figure 212. Data Reception666
Figure 213. Data Transmission667
FMPI2C Slave Mode668
Table 120. FMPI2C Configuration668
Figure 214. Slave Initialization Flowchart670
Figure 215. Transfer Sequence Flowchart for FMPI2C Slave Transmitter672
Figure 216. Transfer Sequence Flowchart for FMPI2C Slave Transmitter673
Figure 217. Transfer Bus Diagrams for FMPI2C Slave Transmitter674
Figure 218. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=0675
Figure 219. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=1676
Figure 220. Transfer Bus Diagrams for FMPI2C Slave Receiver676
FMPI2C Master Mode677
Figure 221. Master Clock Generation678
Table 121. I2C-Smbus Specification Clock Timings679
Figure 222. Master Initialization Flowchart680
Figure 223. 10-Bit Address Read Access with HEAD10R=0680
Figure 224. 10-Bit Address Read Access with HEAD10R=1681
Figure 225. Transfer Sequence Flowchart for FMPI2C Master Transmitter for N≤255 Bytes682
Figure 226. Transfer Sequence Flowchart for FMPI2C Master Transmitter for N>255 Bytes683
Figure 227. Transfer Bus Diagrams for FMPI2C Master Transmitter684
Figure 228. Transfer Sequence Flowchart for FMPI2C Master Receiver for N≤255 Bytes686
Figure 229. Transfer Sequence Flowchart for FMPI2C Master Receiver for N >255 Bytes687
Figure 230. Transfer Bus Diagrams for FMPI2C Master Receiver688
FMPI2C_TIMINGR Register Configuration Examples689
Table 122. Examples of Timing Settings for Fi2Cclk = 8 Mhz689
Table 123. Examples of Timings Settings for Fi2Cclk = 16 Mhz689
Smbus Specific Features690
Table 124. Smbus Timeout Specifications692
Figure 231. Timeout Intervals for T692
Smbus Initialization693
Table 125. Smbus with PEC Configuration694
Table 126. Examples of TIMEOUTA Settings for Various FMPI2CCLK Frequencies694
Smbus: FMPI2C_TIMEOUTR Register Configuration Examples695
Smbus Slave Mode695
Table 127. Examples of TIMEOUTB Settings for Various FMPI2CCLK Frequencies695
Table 128. Examples of TIMEOUTA Settings for Various FMPI2CCLK Frequencies (Max T IDLE = 50 Μs)695
Figure 232. Transfer Sequence Flowchart for Smbus Slave Transmitter N Bytes + PEC696
Figure 233. Transfer Bus Diagrams for Smbus Slave Transmitter (SBC=1)697
Figure 234. Transfer Sequence Flowchart for Smbus Slave Receiver N Bytes + PEC698
Figure 235. Bus Transfer Diagrams for Smbus Slave Receiver (SBC=1)699
Figure 236. Bus Transfer Diagrams for Smbus Master Transmitter700
Error Conditions702
Figure 237. Bus Transfer Diagrams for Smbus Master Receiver702
DMA Requests704
Debug Mode705
FMPI2C Low-Power Modes705
Table 129. Effect of Low-Power Modes on the FMPI2C705
FMPI2C Interrupts706
Table 130. FMPI2C Interrupt Requests706
FMPI2C Registers707
FMPI2C Control Register 1 (FMPI2C_CR1)707
FMPI2C Control Register 2 (FMPI2C_CR2)709
FMPI2C Own Address 1 Register (FMPI2C_OAR1)712
FMPI2C Own Address 2 Register (FMPI2C_OAR2)713
FMPI2C Timing Register (FMPI2C_TIMINGR)714
FMPI2C Timeout Register (FMPI2C_TIMEOUTR)715
FMPI2C Interrupt and Status Register (FMPI2C_ISR)716
FMPI2C Interrupt Clear Register (FMPI2C_ICR)718
FMPI2C PEC Register (FMPI2C_PECR)719
FMPI2C Receive Data Register (FMPI2C_RXDR)720
FMPI2C Transmit Data Register (FMPI2C_TXDR)720
FMPI2C Register Map721
Table 131. FMPI2C Register Map and Reset Values721
Inter-Integrated Circuit723
C Introduction723
I 2 C Main Features724
C Functional Description725
Mode Selection725
Figure 238. I2C Bus Protocol725
I2C Slave Mode726
Figure 239. I2C Block Diagram726
Figure 240. Transfer Sequence Diagram for Slave Transmitter728
I2C Master Mode729
Figure 241. Transfer Sequence Diagram for Slave Receiver729
Figure 242. Transfer Sequence Diagram for Master Transmitter732
Figure 243. Transfer Sequence Diagram for Master Receiver734
Error Conditions735
Programmable Noise Filter736
Table 132. Maximum DNF[3:0] Value to be Compliant with Thd:dat(Max)736
SDA/SCL Line Control737
Smbus737
Table 133. Smbus Vs. I2C738
DMA Requests740
Packet Error Checking741
I 2 C Interrupts742
Table 134. I2C Interrupt Requests742
Figure 244. I2C Interrupt Mapping Diagram743
I 2 C Debug Mode744
I 2 C Registers744
I 2 C Control Register 1 (I2C_CR1)744
I 2 C Control Register 2 (I2C_CR2)746
I 2 C Own Address Register 1 (I2C_OAR1)748
I 2 C Own Address Register 2 (I2C_OAR2)748
C Data Register (I2C_DR)749
C Status Register 1 (I2C_SR1)749
I 2 C Status Register 2 (I2C_SR2)753
I 2 C Clock Control Register (I2C_CCR)754
I 2 C TRISE Register (I2C_TRISE)755
C FLTR Register (I2C_FLTR)756
I2C Register Map757
Table 135. I2C Register Map and Reset Values757
Universal Synchronous Receiver Transmitter (USART) /Universal Asynchronous Receiver Transmitter (UART)758
USART Introduction758
USART Main Features759
USART Implementation760
USART Functional Description760
Table 136. USART Features760
Figure 245. USART Block Diagram762
USART Character Description763
Figure 246. Word Length Programming763
Transmitter764
Figure 247. Configurable Stop Bits765
Figure 248. TC/TXE Behavior When Transmitting766
Receiver767
Figure 249. Start Bit Detection When Oversampling by 16 or 8767
Figure 250. Data Sampling When Oversampling by 16770
Table 137. Noise Detection from Sampled Data771
Figure 251. Data Sampling When Oversampling by 8771
Fractional Baud Rate Generation772
Table 138. Error Calculation for Programmed Baud Rates at F774
USART Receiver Tolerance to Clock Deviation782
Multiprocessor Communication783
Table 150. USART Receiver Tolerance When DIV Fraction Is 0783
Table 151. USART Receiver Tolerance When Div_Fraction Is Different from 0783
Figure 252. Mute Mode Using Idle Line Detection784
Parity Control785
Table 152. Frame Formats785
Figure 253. Mute Mode Using Address Mark Detection785
LIN (Local Interconnection Network) Mode786
Figure 254. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)787
USART Synchronous Mode788
Figure 255. Break Detection in LIN Mode Vs. Framing Error Detection788
Figure 256. USART Example of Synchronous Transmission789
Figure 257. USART Data Clock Timing Diagram (M=0)789
Single-Wire Half-Duplex Communication790
Figure 258. USART Data Clock Timing Diagram (M=1)790
Figure 259. RX Data Setup/Hold Time790
Smartcard791
Figure 260. ISO 7816-3 Asynchronous Protocol791
Figure 261. Parity Error Detection Using the 1.5 Stop Bits792
Irda SIR ENDEC Block793
Figure 262. Irda SIR ENDEC- Block Diagram794
Figure 263. Irda Data Modulation (3/16) -Normal Mode794
Continuous Communication Using DMA795
Figure 264. Transmission Using DMA796
Hardware Flow Control797
Figure 265. Reception Using DMA797
Figure 266. Hardware Flow Control between 2 Usarts797
Figure 267. RTS Flow Control798
Figure 268. CTS Flow Control798
USART Interrupts799
Table 153. USART Interrupt Requests799
USART Registers800
Status Register (USART_SR)800
Figure 269. USART Interrupt Mapping Diagram800
Data Register (USART_DR)803
Baud Rate Register (USART_BRR)803
Control Register 1 (USART_CR1)804
Control Register 2 (USART_CR2)806
Control Register 3 (USART_CR3)807
Guard Time and Prescaler Register (USART_GTPR)809
USART Register Map810
Table 154. USART Register Map and Reset Values810
Serial Peripheral Interface/ Inter-IC Sound (SPI/I2S)811
Introduction811
SPI Main Features812
SPI Extended Features813
I2S Features813
SPI/I2S Implementation813
Table 155. Stm32F412Xx SPI Implementation813
SPI Functional Description814
General Description814
Figure 270. SPI Block Diagram814
Communications between One Master and One Slave815
Figure 271. Full-Duplex Single Master/ Single Slave Application815
Figure 272. Half-Duplex Single Master/ Single Slave Application816
Figure 273. Simplex Single Master/Single Slave Application817
Standard Multi-Slave Communication818
Figure 274. Master and Three Independent Slaves818
Multi-Master Communication819
Slave Select (NSS) Pin Management819
Figure 275. Multi-Master Application819
Figure 276. Hardware/Software Slave Select Management820
Communication Formats821
Figure 277. Data Clock Timing Diagram822
SPI Configuration823
Procedure for Enabling SPI823
Data Transmission and Reception Procedures824
Figure 278. TXE/RXNE/BSY Behavior in Master / Full-Duplex Mode (BIDIMODE=0, RXONLY=0) in the Case of Continuous Transfers825
Procedure for Disabling the SPI826
Figure 279. TXE/RXNE/BSY Behavior in Slave / Full-Duplex Mode (BIDIMODE=0, RXONLY=0) in the Case of Continuous Transfers826
Communication Using DMA (Direct Memory Addressing)827
Figure 280. Transmission Using DMA828
SPI Status Flags829
Figure 281. Reception Using DMA829
SPI Error Flags830
SPI Special Features831
TI Mode831
CRC Calculation832
Figure 282. TI Mode Transfer832
SPI Interrupts834
Table 156. SPI Interrupt Requests834
S Functional Description835
S General Description835
Figure 283. I835
I2S Full-Duplex836
Figure 284. I2S Full-Duplex Block Diagram836
Supported Audio Protocols837
Figure 285. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy, CPOL = 0)838
Figure 286. I 2 S Philips Standard Waveforms (24-Bit Frame with CPOL = 0)838
Figure 287. Transmitting 0X8Eaa33838
Figure 288. Receiving 0X8Eaa33839
Figure 289. I839
Figure 290. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame839
Figure 291. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length with CPOL = 0840
Figure 292. MSB Justified 24-Bit Frame Length with CPOL = 0840
Figure 293. MSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0840
Figure 294. LSB Justified 16-Bit or 32-Bit Full-Accuracy with CPOL = 0841
Figure 295. LSB Justified 24-Bit Frame Length with CPOL = 0841
Figure 296. Operations Required to Transmit 0X3478Ae841
Figure 297. Operations Required to Receive 0X3478Ae842
Figure 298. LSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0842
Figure 299. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame842
Clock Generator843
Figure 300. PCM Standard Waveforms (16-Bit)843
Figure 301. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)843
Figure 302. Audio Sampling Frequency Definition844
Figure 303. I844
Table 157. Audio-Frequency Precision Using Standard 8 Mhz HSE845
I 2 S Master Mode846
I 2 S Slave Mode848
I 2 S Status Flags849
I 2 S Error Flags850
I 2 S Interrupts851
DMA Features851
Table 158. I851
SPI and I 2 S Registers852
SPI Control Register 1 (SPI_CR1) (Not Used in I 2 S Mode)852
SPI Control Register 2 (SPI_CR2)854
SPI Status Register (SPI_SR)855
SPI Data Register (SPI_DR)857
SPI CRC Polynomial Register (SPI_CRCPR) (Not Used in I857
Mode857
SPI RX CRC Register (SPI_RXCRCR) (Not Used in I 2 S Mode)858
SPI TX CRC Register (SPI_TXCRCR) (Not Used in I 2 S Mode)858
SPI_I 2 S Configuration Register (SPI_I2SCFGR)859
SPI_I 2 S Prescaler Register (SPI_I2SPR)860
SPI Register Map862
Table 159. SPI Register Map and Reset Values862
Secure Digital Input/Output Interface (SDIO)863
SDIO Main Features863
SDIO Bus Topology863
Figure 304. "No Response" and "No Data" Operations864
Figure 305. (Multiple) Block Read Operation864
Figure 306. (Multiple) Block Write Operation864
SDIO Functional Description865
Figure 307. Sequential Read Operation865
Figure 308. Sequential Write Operation865
Figure 309. SDIO Block Diagram865
Table 160. SDIO I/O Definitions866
SDIO Adapter867
Figure 310. SDIO Adapter867
Figure 311. Control Unit868
Figure 312. SDIO_CK Clock Dephasing (BYPASS = 0)868
Figure 313. SDIO Adapter Command Path869
Figure 314. Command Path State Machine (SDIO)870
Table 161. Command Format871
Figure 315. SDIO Command Transfer871
Table 162. Short Response Format872
Table 163. Long Response Format872
Table 164. Command Path Status Flags872
Figure 316. Data Path873
Figure 317. Data Path State Machine (DPSM)874
Table 165. Data Token Format875
Table 166. DPSM Flags876
Table 167. Transmit FIFO Status Flags877
Table 168. Receive FIFO Status Flags877
SDIO APB2 Interface878
Card Functional Description879
Card Identification Mode879
Card Reset880
Operating Voltage Range Validation880
Card Identification Process880
Block Write881
Block Read882
Stream Access, Stream Write and Stream Read (Multimediacard Only)882
Erase: Group Erase and Sector Erase884
Wide Bus Selection or Deselection884
Protection Management884
Card Status Register888
Table 169. Card Status888
SD Status Register891
Table 170. SD Status891
Table 171. Speed Class Code Field892
Table 172. Performance Move Field893
Table 173. AU_SIZE Field893
Table 174. Maximum AU Size893
Table 175. Erase Size Field894
Table 176. Erase Timeout Field894
Table 177. Erase Offset Field894
SD I/O Mode895
Commands and Responses896
Table 178. Block-Oriented Write Commands897
Table 179. Block-Oriented Write Protection Commands898
Table 180. Erase Commands898
Table 181. I/O Mode Commands898
Response Formats899
Table 182. Lock Card899
Table 183. Application-Specific Commands899
R1 (Normal Response Command)900
R1B900
R2 (CID, CSD Register)900
Table 184. R1 Response900
Table 185. R2 Response900
R3 (OCR Register)901
R4 (Fast I/O)901
R4B901
Table 186. R3 Response901
Table 187. R4 Response901
Table 188. R4B Response901
R5 (Interrupt Request)902
Table 189. R5 Response902
SDIO I/O Card-Specific Operations903
SDIO I/O Read Wait Operation by SDIO_D2 Signalling903
Table 190. R6 Response903
SDIO Read Wait Operation by Stopping SDIO_CK904
SDIO Suspend/Resume Operation904
SDIO Interrupts904
HW Flow Control904
SDIO Registers905
SDIO Power Control Register (SDIO_POWER)905
SDIO Clock Control Register (SDIO_CLKCR)905
SDIO Argument Register (SDIO_ARG)907
SDIO Command Register (SDIO_CMD)907
SDIO Command Response Register (SDIO_RESPCMD)908
SDIO Response 1908
SDIO Data Timer Register (SDIO_DTIMER)909
Table 191. Response Type and Sdio_Respx Registers909
SDIO Data Length Register (SDIO_DLEN)910
SDIO Data Control Register (SDIO_DCTRL)910
SDIO Data Counter Register (SDIO_DCOUNT)913
SDIO Status Register (SDIO_STA)913
SDIO Interrupt Clear Register (SDIO_ICR)914
SDIO Mask Register (SDIO_MASK)916
SDIO FIFO Counter Register (SDIO_FIFOCNT)918
SDIO Data FIFO Register (SDIO_FIFO)919
SDIO Register Map920
Table 192. SDIO Register Map920
Controller Area Network (Bxcan)922
Introduction922
Bxcan Main Features922
Bxcan General Description923
CAN 2.0B Active Core923
Control, Status and Configuration Registers923
Tx Mailboxes923
Figure 318. CAN Network Topology923
Acceptance Filters924
Figure 319. Dual-CAN Block Diagram924
Bxcan Operating Modes925
Initialization Mode925
Normal Mode925
Sleep Mode (Low-Power)926
Figure 320. Bxcan Operating Modes926
Test Mode927
Silent Mode927
Loop Back Mode927
Figure 321. Bxcan in Silent Mode927
Figure 322. Bxcan in Loop Back Mode927
Loop Back Combined with Silent Mode928
Behavior in Debug Mode928
Bxcan Functional Description928
Transmission Handling928
Figure 323. Bxcan in Combined Mode928
Time Triggered Communication Mode930
Reception Handling930
Figure 324. Transmit Mailbox States930
Figure 325. Receive FIFO States931
Identifier Filtering932
Figure 326. Filter Bank Scale Configuration - Register Organization934
Figure 327. Example of Filter Numbering935
Message Storage936
Figure 328. Filtering Mechanism - Example936
Table 193. Transmit Mailbox Mapping937
Table 194. Receive Mailbox Mapping937
Figure 329. CAN Error State Diagram937
Error Management938
Bit Timing938
Figure 330. Bit Timing939
Figure 331. CAN Frames940
Bxcan Interrupts941
Figure 332. Event Flags and Interrupt Generation941
CAN Registers942
Register Access Protection942
CAN Control and Status Registers942
CAN Mailbox Registers952
Figure 333. CAN Mailbox Registers952
CAN Filter Registers959
Bxcan Register Map963
Table 195. Bxcan Register Map and Reset Values963
USB On-The-Go Full-Speed (OTG_FS)967
Introduction967
Table 196. OTG_FS Speeds Supported967
OTG_FS Main Features968
General Features968
Host-Mode Features969
Peripheral-Mode Features969
Split Rail for USB969
OTG_FS Implementation970
Table 197. OTG_FS Implementation970
OTG_FS Functional Description971
OTG_FS Block Diagram971
OTG_FS Pin and Internal Signals971
Table 198. OTG_FS Input/Output Pins971
Figure 334. OTG_FS Full-Speed Block Diagram971
OTG_FS Core972
Embedded Full-Speed OTG PHY Connected to OTG_FS972
Table 199. OTG_FS Input/Output Signals972
OTG Detections973
OTG_FS Dual Role Device (DRD)973
ID Line Detection973
Figure 335. OTG_FS A-B Device Connection973
HNP Dual Role Device974
SRP Dual Role Device974
OTG_FS as a USB Peripheral974
SRP-Capable Peripheral975
Peripheral States975
Figure 336. OTG_FS Peripheral-Only Connection975
Peripheral Endpoints976
OTG_FS as a USB Host978
SRP-Capable Host979
USB Host States979
Figure 337. OTG_FS Host-Only Connection979
Host Channels981
Host Scheduler982
OTG_FS SOF Trigger983
Host Sofs983
Peripheral Sofs983
Figure 338. SOF Connectivity (SOF Trigger Output to TIM and ITR1 Connection)983
OTG_FS Low-Power Modes984
Table 200. Compatibility of STM32 Low Power Modes with the OTG984
OTG_FS Dynamic Update of the OTG_HFIR Register985
OTG_FS Data Fifos985
Figure 339. Updating OTG_HFIR Dynamically (RLDCTRL = 1)985
Peripheral FIFO Architecture986
Figure 340. Device-Mode FIFO Address Mapping and AHB FIFO Access Mapping986
Host FIFO Architecture987
Figure 341. Host-Mode FIFO Address Mapping and AHB FIFO Access Mapping987
FIFO RAM Allocation988
OTG_FS System Performance990
OTG_FS Interrupts990
Figure 342. Interrupt Hierarchy991
OTG_FS Control and Status Registers992
CSR Memory Map992
Table 201. Core Global Control and Status Registers (Csrs)992
Table 202. Host-Mode Control and Status Registers (Csrs)993
Table 203. Device-Mode Control and Status Registers994
OTG_FS Registers996
Table 204. Data FIFO (DFIFO) Access Register Map996
Table 205. Power and Clock Gating Control and Status Registers996
OTG Control and Status Register (OTG_GOTGCTL)997
OTG Interrupt Register (OTG_GOTGINT)1000
OTG AHB Configuration Register (OTG_GAHBCFG)1001
OTG USB Configuration Register (OTG_GUSBCFG)1002
Table 206. TRDT Values (FS)1003
OTG Reset Register (OTG_GRSTCTL)1004
OTG Core Interrupt Register (OTG_GINTSTS)1006
OTG Interrupt Mask Register (OTG_GINTMSK)1010
OTG Receive Status Debug Read Register (OTG_GRXSTSR)1013
OTG Receive Status Debug Read [Alternate] (OTG_GRXSTSR)1014
OTG Status Read and Pop Registers (OTG_GRXSTSP)1015
OTG Status Read and Pop Registers [Alternate] (OTG_GRXSTSP)1016
OTG Receive FIFO Size Register (OTG_GRXFSIZ)1017
OTG Host Non-Periodic Transmit FIFO Size Register (Otg_Hnptxfsiz)/Endpoint 0 Transmit FIFO Size1017
(Otg_Dieptxf0)1017
29.15.14 OTG Non-Periodic Transmit Fifo/Queue Status Register1018
(Otg_Hnptxsts)1018
OTG General Core Configuration Register (OTG_GCCFG)1019
OTG Core ID Register (OTG_CID)1021
OTG Core LPM Configuration Register (OTG_GLPMCFG)1021
29.15.18 OTG Host Periodic Transmit FIFO Size Register1025
(Otg_Hptxfsiz)1025
29.15.19 OTG Device in Endpoint Transmit FIFO X Size Register1025
(Otg_Dieptxfx)1025
29.15.20 Host-Mode Registers1026
OTG Host Configuration Register (OTG_HCFG)1026
OTG Host Frame Interval Register (OTG_HFIR)1027
29.15.23 OTG Host Frame Number/Frame Time Remaining Register1028
(Otg_Hfnum)1028
29.15.24 Otg_Host Periodic Transmit Fifo/Queue Status Register1028
(Otg_Hptxsts)1028
OTG Host All Channels Interrupt Register (OTG_HAINT)1029
29.15.26 OTG Host All Channels Interrupt Mask Register1030
(Otg_Haintmsk)1030
OTG Host Port Control and Status Register (OTG_HPRT)1031
OTG Host Channel X Characteristics Register (Otg_Hccharx)1033
OTG Host Channel X Interrupt Register (Otg_Hcintx)1034
OTG Host Channel X Interrupt Mask Register (Otg_Hcintmskx)1035
OTG Host Channel X Transfer Size Register (Otg_Hctsizx)1036
29.15.32 Device-Mode Registers1037
OTG Device Configuration Register (OTG_DCFG)1037
OTG Device Control Register (OTG_DCTL)1038
Table 207. Minimum Duration for Soft Disconnect1040
OTG Device Status Register (OTG_DSTS)1041
29.15.36 OTG Device in Endpoint Common Interrupt Mask Register1042
(Otg_Diepmsk)1042
29.15.37 OTG Device out Endpoint Common Interrupt Mask Register1043
(Otg_Doepmsk)1043
OTG Device All Endpoints Interrupt Register (OTG_DAINT)1044
29.15.39 OTG All Endpoints Interrupt Mask Register1045
(Otg_Daintmsk)1045
OTG Device1045
(Otg_Dvbusdis)1045
BUS Discharge Time Register1046
OTG Device1046
(Otg_Dvbuspulse)1046
BUS Pulsing Time Register1046
29.15.42 OTG Device in Endpoint FIFO Empty Interrupt Mask Register1046
(Otg_Diepempmsk)1046
29.15.43 OTG Device Control in Endpoint 0 Control Register1047
(Otg_Diepctl0)1047
OTG Device in Endpoint X Control Register (Otg_Diepctlx)1048
OTG Device in Endpoint X Interrupt Register (Otg_Diepintx)1051
29.15.46 OTG Device in Endpoint 0 Transfer Size Register1052
(Otg_Dieptsiz0)1052
29.15.47 OTG Device in Endpoint Transmit FIFO Status Register1053
(Otg_Dtxfstsx)1053
OTG Device in Endpoint X Transfer Size Register (Otg_Dieptsizx)1054
29.15.49 OTG Device Control out Endpoint 0 Control Register1055
(Otg_Doepctl0)1055
OTG Device out Endpoint X Interrupt Register (Otg_Doepintx)1056
29.15.51 OTG Device out Endpoint 0 Transfer Size Register1058
(Otg_Doeptsiz0)1058
(Otg_Doepctlx)1059
(Otg_Doeptsizx)1061
OTG Power and Clock Gating Control Register (OTG_PCGCCTL)1062
29.15.55 OTG_FS Register Map1063
Table 208. OTG_FS Register Map and Reset Values1063
OTG_FS Programming Model1071
Core Initialization1071
Host Initialization1072
Device Initialization1072
Host Programming Model1073
Figure 343. Transmit FIFO Write Task1074
Figure 344. Receive FIFO Read Task1075
Figure 345. Normal Bulk/Control OUT/SETUP1076
Figure 346. Bulk/Control in Transactions1080
Figure 347. Normal Interrupt out1083
Figure 348. Normal Interrupt in1088
Figure 349. Isochronous out Transactions1090
Figure 350. Isochronous in Transactions1093
Device Programming Model1094
Figure 351. Receive FIFO Packet Read1097
Figure 352. Processing a SETUP Packet1099
Figure 353. Bulk out Transaction1106
Worst Case Response Time1115
Figure 354. TRDT Max Timing Case1116
OTG Programming Model1117
Figure 355. A-Device SRP1117
Figure 356. B-Device SRP1118
Figure 357. A-Device HNP1119
Figure 358. B-Device HNP1121
Debug Support (DBG)1123
Overview1123
Reference Arm® Documentation1124
SWJ Debug Port (Serial Wire and JTAG)1124
Mechanism to Select the JTAG-DP or the SW-DP1125
Pinout and Debug Port Pins1125
Figure 360. SWJ Debug Port1125
SWJ Debug Port Pins1126
Flexible SWJ-DP Pin Assignment1126
Table 209. SWJ Debug Port Pins1126
Table 210. Flexible SWJ-DP Pin Assignment1126
Internal Pull-Up and Pull-Down on JTAG Pins1127
Using Serial Wire and Releasing the Unused Debug Pins as Gpios1128
JTAG TAP Connection1128
Figure 361. JTAG TAP Connections1129
ID Codes and Locking Mechanism1130
MCU Device ID Code1130
Boundary Scan TAP1130
Cortex1131
Cortex ® -M4 with FPU JEDEC-106 ID Code1131
JTAG Debug Port1131
Table 211. JTAG Debug Port Data Registers1131
Table 212. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]1132
SW Debug Port1133
SW Protocol Introduction1133
SW Protocol Sequence1133
Table 213. Packet Request (8-Bits)1133
SW-DP State Machine (Reset, Idle States, ID Code)1134
DP and AP Read/Write Accesses1134
Table 214. ACK Response (3 Bits)1134
Table 215. DATA Transfer (33 Bits)1134
SW-DP Registers1135
Table 216. SW-DP Registers1135
SW-AP Registers1136
AHB-AP (AHB Access Port) - Valid for both JTAG-DP and SW-DP1136
Table 217. Cortex ® -M4 with FPU AHB-AP Registers1136
Core Debug1137
Table 218. Core Debug Registers1137
Capability of the Debugger Host to Connect under System Reset1138
FPB (Flash Patch Breakpoint)1138
DWT (Data Watchpoint Trigger)1139
ITM (Instrumentation Trace Macrocell)1139
General Description1139
Time Stamp Packets, Synchronization and Overflow Packets1139
Table 219. Main ITM Registers1140
ETM (Embedded Trace Macrocell)1141
General Description1141
Signal Protocol, Packet Types1141
Main ETM Registers1141
Configuration Example1142
MCU Debug Component (DBGMCU)1142
Debug Support for Low-Power Modes1142
Table 220. Main ETM Registers1142
Debug Support for Timers, Watchdog, Bxcan and I1143
11431143
Debug MCU Configuration Register1143
Debug MCU APB1 Freeze Register (DBGMCU_APB1_FZ)1144
Debug MCU APB2 Freeze Register (DBGMCU_APB2_FZ)1146
TPIU (Trace Port Interface Unit)1146
Introduction1146
Figure 362. TPIU Block Diagram1147
TRACE Pin Assignment1148
Table 221. Asynchronous TRACE Pin Assignment1148
Table 222. Synchronous TRACE Pin Assignment1148
TPUI Formatter1149
Table 223. Flexible TRACE Pin Assignment1149
TPUI Frame Synchronization Packets1150
Transmission of the Synchronization Frame Packet1150
Synchronous Mode1150
Asynchronous Mode1151
TRACECLKIN Connection1151
TPIU Registers1151
Table 224. Important TPIU Registers1151
30.17.10 Example of Configuration1152
DBG Register Map1153
Table 225. DBG Register Map and Reset Values1153
Device Electronic Signature1154
Unique Device ID Register (96 Bits)1154
Flash Size1155
Package Data Register1155
Revision History1157
Table 148. Error Calculation for Programmed Baud Rates at F1157
Table 149. Error Calculation for Programmed Baud Rates at F PCLK = 100 Mhz or F PCLK = 50 Mhz1157
Table 226. Document Revision History1157

Table of Contents

Related product manuals