RM0402 Rev 6 193/1163
RM0402 System configuration controller (SYSCFG)
194
8.2.9 SYSCFG configuration register (SYSCFG_CFGR)
Address offset: 0x2C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
15141312111098765432 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. I2CFMP1_SDA I2CFMP1_SCL
rw rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 I2CFMP1_SDA
Set and cleared by software. When this bit is set, it forces FM+ drive capability on
I2CFMP1_SDA pin selected through GPIO port mode register and GPIO alternate
function selection bits.
Bit 0 I2CFMP1_SCL
Set and cleared by software. When this bit is set, it forces FM+ drive capability on
I2CFMP1_SCL pin selected through GPIO port mode register and GPIO alternate
function selection bits.