ST STM32F412 User Manual

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402
702/1163 RM0402 Rev 6
Figure 237. Bus transfer diagrams for SMBus master receiver
23.4.15 Error conditions
The following errors are the error conditions which may cause communication to fail.
Bus error (BERR)
A bus error is detected when a START or a STOP condition is detected and is not located
after a multiple of 9 SCL clock pulses. A START or a STOP condition is detected when a
SDA edge occurs while SCL is high.
The bus error flag is set only if the FMPI2C is involved in the transfer as master or
addressed slave (i.e not during the address phase in slave mode).
In case of a misplaced START or RESTART detection in slave mode, the FMPI2C enters
address recognition state like for a correct START condition.
MS19872V2
Example SMBus master receiver 2 bytes + PEC, automatic end mode (STOP)
Address
S
INIT: program Slave address, program NBYTES = 3, AUTOEND=1, set PECBYTE, set START
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: rd PEC
A
data1
A
RXNE RXNE
data2
A
NBYTES
NA
legend:
transmission
reception
SCL stretch
3VE1VE
xx 3
INIT
Example SMBus master receiver 2 bytes + PEC, software end mode (RESTART)
Address
S
INIT: program Slave address, program NBYTES = 3, AUTOEND=0, set PECBYTE, set START
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: read PEC
EV4: TC ISR: program Slave address, program NBYTES = N, set START
A
data1
A
RXNE RXNE
data2
A
NBYTES
Restart
legend:
transmission
reception
SCL stretch
EV1 EV2
xx
INIT
Address
N
PEC
P
RXNE
EV2
NA
PEC
RXNE
3
EV3
TC
EV4

ST STM32F412 Specifications

General

Brand	ST
Model	STM32F412
Category	Microcontrollers
Language	English