ST STM32F412 User Manual

RM0402 Rev 6 389/1163
RM0402 Digital filter for sigma delta modulators (DFSDM)
400
14.8.6 DFSDM filter x control register (DFSDM_FLTxFCR)
Address offset: 0x114 + 0x80 * x, (x = 0 to 1)
Reset value: 0x0000 0000
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 JCHG[3:0]: Injected channel group selection
JCHG[y]=0: channel y is not part of the injected group
JCHG[y]=1: channel y is part of the injected group
If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel
(channel 0, if selected) is converted first and the sequence ends at the highest selected channel.
If JSCAN=0, then only one channel is converted from the selected channels, and the channel
selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to
the lowest selected channel.
At least one channel must always be selected for the injected group. Writes causing all JCHG bits to
be zero are ignored.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FORD[2:0] Res. Res. Res. FOSR[9:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. IOSR[7:0]
rw rw rw rw rw rw rw rw
Bits 31:29 FORD[2:0]: Sinc filter order
0: FastSinc filter type
1: Sinc
1
filter type
2: Sinc
2
filter type
3: Sinc
3
filter type
4: Sinc
4
filter type
5: Sinc
5
filter type
6-7: Reserved
Sinc
x
filter type transfer function:
FastSinc filter type transfer function:
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
Bits 28:26 Reserved, must be kept at reset value.
Hz()
1z
FOSR–
–
1z
1–
–
-----------------------------



x
=
Hz()
1z
FOSR–
–
1z
1–
–
-----------------------------



2
1z
2FOSR⋅()–
+()⋅=

ST STM32F412 Specifications

General

Brand	ST
Model	STM32F412
Category	Microcontrollers
Language	English