ST STM32F412

RM0402 Rev 6 603/1163
RM0402 Basic timers (TIM6/7)
604
19.4.7 TIM6/7 prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
19.4.8 TIM6/7 auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0xFFFF
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency (CK_CNT) is equal to f
CK_PSC
/ (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 15:0 ARR[15:0]: Auto-reload value
ARR is the value to be loaded into the actual auto-reload register.
Refer to Section 19.3.1: Time-base unit on page 593 for more details about ARR update and
behavior.
The counter is blocked while the auto-reload value is null.