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Serial peripheral interface/ inter-IC sound (SPI/I2S) RM0402

858/1163 RM0402 Rev 6

26.7.6 SPI RX CRC register (SPI_RXCRCR) (not used in I

S mode)

Address offset: 0x14

Reset value: 0x0000

26.7.7 SPI TX CRC register (SPI_TXCRCR) (not used in I

S mode)

Address offset: 0x18

Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RXCRC[15:0]

r r r r r r r r r r r r r r r r

Bits 15:0 RXCRC[15:0]: Rx CRC register

When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of

the subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1

the SPI_CRCPR register.

Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (DFF

bit of SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard.

The entire 16-bits of this register are considered when a 16-bit data frame format is selected

(DFF bit of the SPI_CR1 register is set). CRC calculation is done based on any CRC16

standard.

Note: A read to this register when the BSY Flag is set could return an incorrect value.These

bits are not used for I

S mode.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TXCRC[15:0]

r r r r r r r r r r r r r r r r

Bits 15:0 TXCRC[15:0]: Tx CRC register

When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of

the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1

is written to 1. The CRC is calculated serially using the polynomial programmed in the

SPI_CRCPR register.