RM0402 Rev 6 263/1163
RM0402 Flexible static memory controller (FSMC)
287
Note: The FSMC_BWTRx register is valid only if the Extended mode is set (mode B), otherwise its
content is don’t care.
Mode C - NOR Flash - OE toggling
Figure 40. Mode C read access waveforms
Table 57. FSMC_BWTRx bitfields (mode 2/B)
Bit number Bit name Value to set
31:30 Reserved 0x0
29:28 ACCMOD 0x1 if Extended mode is set
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST
Duration of the access second phase (DATAST HCLK cycles) for
write accesses.
7:4 ADDHLD Don’t care
3:0 ADDSET
Duration of the access first phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 0.
A[25:0]
NOE
ADDSET DATAST
Memory transaction
NEx
D[15:0]
HCLK cycles HCLK cycles
NWE
NADV
data driven
by memory
MS34484V1
High
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