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RM0402 Rev 6 719/1163

RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface

722

23.7.9 FMPI2C PEC register (FMPI2C_PECR)

Address offset: 0x20

Reset value: 0x0000 0000

Access: No wait states

Note: If the SMBus feature is not supported, this register is reserved and forced by hardware to

“0x00000000”. Refer to Section 23.3: FMPI2C implementation.

Bit 10 OVRCF: Overrun/Underrun flag clear

Writing 1 to this bit clears the OVR flag in the FMPI2C_ISR register.

Bit 9 ARLOCF: Arbitration lost flag clear

Writing 1 to this bit clears the ARLO flag in the FMPI2C_ISR register.

Bit 8 BERRCF: Bus error flag clear

Writing 1 to this bit clears the BERRF flag in the FMPI2C_ISR register.

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 STOPCF: STOP detection flag clear

Writing 1 to this bit clears the STOPF flag in the FMPI2C_ISR register.

Bit 4 NACKCF: Not Acknowledge flag clear

Writing 1 to this bit clears the NACKF flag in FMPI2C_ISR register.

Bit 3 ADDRCF: Address matched flag clear

Writing 1 to this bit clears the ADDR flag in the FMPI2C_ISR register. Writing 1 to this bit

also clears the START bit in the FMPI2C_CR2 register.

Bits 2:0 Reserved, must be kept at reset value.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

1514131211109876543210

Res. Res. Res. Res. Res. Res. Res. Res. PEC[7:0]

rrrrrrrr

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PEC[7:0] Packet error checking register

This field contains the internal PEC when PECEN=1.

The PEC is cleared by hardware when PE=0.

ST STM32F412 User Manual

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