ST STM32F412 User Manual

RM0402 Rev 6 153/1163
RM0402 Reset and clock control (RCC) for STM32F412xx
166
6.3.19 RCC APB2 peripheral clock enabled in low power mode register
(RCC_APB2LPENR)
Address offset: 0x64
Reset value: 0x0117 F933
Access: no wait state, word, half-word and byte access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res.
DFSDM1
LPEN
Res. Res. Res.
SPI5
LPEN
Res.
TIM11
LPEN
TIM10
LPEN
TIM9
LPEN
rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTIT
EN
SYSC
FG
LPEN
SPI4LP
EN
SPI1
LPEN
SDIO
LPEN
Res. Res.
ADC1
LPEN
Res. Res.
USART6
LPEN
USART1
LPEN
Res. Res.
TIM8
LPEN
TIM1
LPEN
rw rw rw rw rw rw rw rw rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 DFSDM1LPEN: DFSDM1 clock enable during Sleep mode
This bit is set and cleared by software
0: DFSDM1 clock disabled during Sleep mode
1: DFSDM1 clock enabled during Sleep mode
Bits 23:21 Reserved, must be kept at reset value.
Bit 20 SPI5LPEN: SPI5 clock enable during Sleep mode
This bit is set and cleared by software
0: SPI5 clock disabled during Sleep mode
1: SPI5 clock enabled during Sleep mode
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11LPEN: TIM11 clock enable during Sleep mode
Set and cleared by software.
0: TIM11 clock disabled during Sleep mode
1: TIM11 clock enabled during Sleep mode
Bit 17 TIM10LPEN: TIM10 clock enable during Sleep mode
Set and cleared by software.
0: TIM10 clock disabled during Sleep mode
1: TIM10 clock enabled during Sleep mode
Bit 16 TIM9LPEN: TIM9 clock enable during sleep mode
Set and cleared by software.
0: TIM9 clock disabled during Sleep mode
1: TIM9 clock enabled during Sleep mode
Bit 15 EXTITEN: EXTIT APB and SYSCTRL PFREE clock enable during Sleep mode
Set and cleared by software.
0: EXTIT APB and SYSCTRL PFREE clock disabled during Sleep mode
1: EXTIT APB and SYSCTRL PFREE clock enabled during Sleep mode

ST STM32F412 Specifications

General

Brand	ST
Model	STM32F412
Category	Microcontrollers
Language	English