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ST STM32F412 User Manual
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Fast-mode Plus
Inter-integrated ci
rcuit (FMPI2C) interface
RM0402
678/1
163
RM0402 Rev 6
Figure 221. Master clock
generation
Caution:
In order to be I
2
C or SMBus compliant, the master clo
ck must respect the timi
ngs given the
table below
.
MS19858V1
t
SYNC1
SCL high level detected
SCLH counter starts
SCLH
SCL
SCL master clock generation
SCL released
SCL low level detected
SCLL counter starts
SCL driven low
SCLL
t
SYNC2
SCL master clock synchronization
SCLL
SCL driven low by
another device
SCL low level detected
SCLL counter starts
SCL released
SCLH
SCLH
SCL high level detected
SCLH counter starts
SCL high level detected
SCLH counter starts
SCL low level detected
SCLL counter starts
SCLL
SCL driven low by
another device
SCLH
SCL high level detected
SCLH counter starts
677
679
Table of Contents
Table of Contents
2
SYSCFG External Interrupt Configuration Register
4
Documentation Conventions
45
General Information
45
List of Abbreviations for Registers
45
Glossary
46
Availability of Peripherals
46
System and Memory Overview
47
System Architecture
47
Figure 1. System Architecture
47
I-Bus
48
D-Bus
48
S-Bus
48
DMA Memory Bus
48
DMA Peripheral Bus
48
Busmatrix
48
AHB/APB Bridges (APB)
48
Memory Organization
49
Introduction
49
Memory Map and Register Boundary Addresses
50
Figure 2. Memory Map
50
Table 1. Register Boundary Addresses
51
Embedded SRAM
53
Flash Memory Overview
54
Bit Banding
54
Boot Configuration
55
Table 2. Boot Modes
55
Table 3. Embedded Bootloader Interfaces
56
Table 4. Memory Mapping Vs. Boot Mode/Physical Remap in Stm32F412Xx
56
Embedded Flash Memory Interface
58
Introduction
58
Main Features
58
Figure 3. Flash Memory Interface Connection Inside System Architecture
58
Embedded Flash Memory
59
Table 5. Flash Module Organization
59
Read Interface
60
Relation between CPU Clock Frequency and Flash Memory Read Time
60
Table 6. Number of Wait States According to CPU Clock (HCLK) Frequency
60
Adaptive Real-Time Memory Accelerator (ART Accelerator™)
61
Figure 4. Sequential 32-Bit Instruction Execution
62
Erase and Program Operations
63
Unlocking the Flash Control Register
63
Program/Erase Parallelism
64
Erase
64
Table 7. Program/Erase Parallelism
64
Programming
65
Interrupts
66
Option Bytes
66
Description of User Option Bytes
66
Table 8. Flash Interrupt Request
66
Table 9. Option Byte Organization
66
Table 10. Description of the Option Bytes
67
Programming User Option Bytes
68
Read Protection (RDP)
68
Write Protections
70
Table 11. Access Versus Read Protection Level
70
Figure 5. RDP Levels
70
Proprietary Code Readout Protection (PCROP)
71
Figure 6. PCROP Levels
72
One-Time Programmable Bytes
73
Table 12. OTP Area Organization
73
Flash Interface Registers
74
Flash Access Control Register (FLASH_ACR)
74
Flash Key Register (FLASH_KEYR)
75
Flash Option Key Register (FLASH_OPTKEYR)
75
Flash Status Register (FLASH_SR)
76
Flash Control Register (FLASH_CR)
77
Flash Option Control Register (FLASH_OPTCR)
78
Flash Interface Register Map
81
Table 13. Flash Register Map and Reset Values
81
CRC Calculation Unit
82
CRC Introduction
82
CRC Main Features
82
CRC Functional Description
82
Figure 7. CRC Calculation Unit Block Diagram
82
CRC Registers
83
Data Register (CRC_DR)
83
Independent Data Register (CRC_IDR)
84
Control Register (CRC_CR)
84
CRC Register Map
85
Table 14. CRC Calculation Unit Register Map and Reset Values
85
Power Controller (PWR)
86
Power Supplies
86
Independent A/D Converter Supply and Reference Voltage
87
Battery Backup Domain
87
Figure 8. Power Supply Overview
87
Voltage Regulator
89
Power Supply Supervisor
90
Power-On Reset (Por)/Power-Down Reset (PDR)
90
Brownout Reset (BOR)
90
Figure 9. Power-On Reset/Power-Down Reset Waveform
90
Programmable Voltage Detector (PVD)
91
Figure 10. BOR Thresholds
91
Low-Power Modes
92
Figure 11. PVD Thresholds
92
Slowing down System Clocks
94
Peripheral Clock Gating
94
Table 15. Low-Power Mode Summary
94
Sleep Mode
95
Table 16. Sleep-Now Entry and Exit
95
Table 17. Sleep-On-Exit Entry and Exit
95
Batch Acquisition Mode
96
Table 18. BAM-Now Entry and Exit
96
Stop Mode
97
Table 19. BAM-On-Exit Entry and Exit
97
Table 20. Stop Operating Modes
98
Table 21. Stop Mode Entry and Exit
99
Standby Mode
100
Programming the RTC Alternate Functions to Wake up the Device from the Stop and Standby Modes
101
Table 22. Standby Mode Entry and Exit
101
Power Control Registers
104
PWR Power Control Register (PWR_CR)
104
PWR Power Control/Status Register (PWR_CSR)
106
PWR Register Map
108
Table 23. PWR - Register Map and Reset Values
108
Reset and Clock Control (RCC) for Stm32F412Xx
109
Reset
109
System Reset
109
Power Reset
110
Figure 12. Simplified Diagram of the Reset Circuit
110
Backup Domain Reset
111
Clocks
111
Figure 13. Clock Tree
112
HSE Clock
113
HSI Clock
114
Figure 14. HSE/ LSE Clock Sources
114
PLL Configuration
115
LSE Clock
115
LSI Clock
116
System Clock (SYSCLK) Selection
116
Clock Security System (CSS)
116
RTC/AWU Clock
117
Watchdog Clock
117
Clock-Out Capability
118
Internal/External Clock Measurement Using TIM5/TIM11
118
Figure 15. Frequency Measurement with TIM5 in Input Capture Mode
119
Figure 16. Frequency Measurement with TIM11 in Input Capture Mode
120
RCC Registers
121
RCC Clock Control Register (RCC_CR)
121
RCC PLL Configuration Register (RCC_PLLCFGR)
123
RCC Clock Configuration Register (RCC_CFGR)
125
RCC Clock Interrupt Register (RCC_CIR)
128
RCC AHB1 Peripheral Reset Register (RCC_AHB1RSTR)
130
RCC AHB2 Peripheral Reset Register (RCC_AHB2RSTR)
132
RCC AHB3 Peripheral Reset Register (RCC_AHB3RSTR)
133
RCC APB1 Peripheral Reset Register for (RCC_APB1RSTR)
133
RCC APB2 Peripheral Reset Register (RCC_APB2RSTR)
136
RCC AHB1 Peripheral Clock Enable Register (RCC_AHB1ENR)
138
RCC AHB2 Peripheral Clock Enable Register (RCC_AHB2ENR)
140
RCC AHB3 Peripheral Clock Enable Register (RCC_AHB3ENR)
141
RCC APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
141
RCC APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
144
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB1LPENR)
146
RCC AHB2 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB2LPENR)
148
RCC AHB3 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB3LPENR)
148
RCC APB1 Peripheral Clock Enable in Low Power Mode Register (RCC_APB1LPENR)
150
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register (RCC_APB2LPENR)
153
RCC Backup Domain Control Register (RCC_BDCR)
155
RCC Clock Control & Status Register (RCC_CSR)
156
RCC Spread Spectrum Clock Generation Register (RCC_SSCGR)
158
RCC PLLI2S Configuration Register (RCC_PLLI2SCFGR)
159
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)
161
RCC Clocks Gated Enable Register (CKGATENR)
162
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR2)
163
RCC Register Map
164
Table 24. RCC Register Map and Reset Values for Stm32F412Xx
164
General-Purpose I/Os (GPIO)
167
GPIO Introduction
167
GPIO Main Features
167
GPIO Functional Description
167
Table 25. Port Bit Configuration Table
168
Figure 17. Basic Structure of a Five-Volt Tolerant I/O Port Bit
168
General-Purpose I/O (GPIO)
169
I/O Pin Multiplexer and Mapping
170
Table 26. Flexible SWJ-DP Pin Assignment
171
Figure 18. Selecting an Alternate Function on Stm32F412Xx
172
I/O Port Control Registers
173
I/O Port Data Registers
173
I/O Data Bitwise Handling
173
GPIO Locking Mechanism
173
I/O Alternate Function Input/Output
174
External Interrupt/Wakeup Lines
174
Input Configuration
174
Output Configuration
175
Figure 19. Input Floating/Pull Up/Pull down Configurations
175
Alternate Function Configuration
176
Figure 20. Output Configuration
176
Figure 21. Alternate Function Configuration
176
Analog Configuration
177
Using the OSC32_IN/OSC32_OUT Pins as GPIO PC14/PC15
177
Port Pins
177
Using the OSC_IN/OSC_OUT Pins as GPIO PH0/PH1 Port Pins
177
Figure 22. High Impedance-Analog Configuration
177
Selection of RTC Additional Functions
178
Table 27. RTC Additional Functions
178
GPIO Registers
179
GPIO Port Mode Register (Gpiox_Moder) (X = a
179
GPIO Port Output Type Register (Gpiox_Otyper)
179
(X = a
179
GPIO Port Output Speed Register (Gpiox_Ospeedr)
180
(X = a
180
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupdr)
180
GPIO Port Input Data Register (Gpiox_Idr) (X = a
181
GPIO Port Output Data Register (Gpiox_Odr) (X = a
181
GPIO Port Bit Set/Reset Register (Gpiox_Bsrr) (X = a
181
GPIO Port Configuration Lock Register (Gpiox_Lckr)
182
(X = a
182
GPIO Alternate Function Low Register (Gpiox_Afrl) (X = a
183
(X = a
184
GPIO Register Map
184
Table 28. GPIO Register Map and Reset Values
184
System Configuration Controller (SYSCFG)
187
I/O Compensation Cell
187
SYSCFG Registers
187
SYSCFG Memory Remap Register (SYSCFG_MEMRMP)
187
SYSCFG Peripheral Mode Configuration Register (SYSCFG_PMC)
188
SYSCFG External Interrupt Configuration Register 1
189
(Syscfg_Exticr1)
189
(Syscfg_Exticr2)
189
SYSCFG External Interrupt Configuration Register 3
190
(Syscfg_Exticr3)
190
(Syscfg_Exticr4)
191
SYSCFG Configuration Register 2 (SYSCFG_CFGR2)
191
Compensation Cell Control Register (SYSCFG_CMPCR)
192
SYSCFG Configuration Register (SYSCFG_CFGR)
193
SYSCFG Register Map
194
Table 29. SYSCFG Register Map and Reset Values
194
Direct Memory Access Controller (DMA)
195
DMA Introduction
195
DMA Main Features
195
DMA Functional Description
197
DMA Block Diagram
197
DMA Overview
197
Figure 23. DMA Block Diagram
197
DMA Transactions
198
Channel Selection
198
Figure 24. Channel Selection
198
Table 30. DMA1 Request Mapping
199
Table 31. DMA2 Request Mapping
199
Arbiter
200
DMA Streams
200
Source, Destination and Transfer Modes
200
Table 32. Source and Destination Address
200
Figure 25. Peripheral-To-Memory Mode
202
Figure 26. Memory-To-Peripheral Mode
203
Pointer Incrementation
204
Figure 27. Memory-To-Memory Mode
204
Circular Mode
205
Double-Buffer Mode
205
Programmable Data Width, Packing/Unpacking, Endianness
206
Table 33. Source and Destination Address Registers in Double-Buffer Mode (DBM = 1)
206
Single and Burst Transfers
207
Table 34. Packing/Unpacking and Endian Behavior (Bit PINC = MINC = 1)
207
Table 35. Restriction on NDT Versus PSIZE and MSIZE
207
Fifo
208
Figure 28. FIFO Structure
209
Table 36. FIFO Threshold Configurations
210
DMA Transfer Completion
211
DMA Transfer Suspension
212
Flow Controller
213
Summary of the Possible DMA Configurations
214
Stream Configuration Procedure
214
Table 37. Possible DMA Configurations
214
Error Management
215
DMA Interrupts
216
Table 38. DMA Interrupt Requests
216
DMA Registers
217
DMA Low Interrupt Status Register (DMA_LISR)
217
DMA High Interrupt Status Register (DMA_HISR)
218
DMA Low Interrupt Flag Clear Register (DMA_LIFCR)
219
DMA High Interrupt Flag Clear Register (DMA_HIFCR)
219
DMA Stream X Configuration Register (Dma_Sxcr)
220
DMA Stream X Number of Data Register (Dma_Sxndtr)
223
DMA Stream X Peripheral Address Register (Dma_Sxpar)
224
DMA Stream X Memory 0 Address Register (Dma_Sxm0Ar)
224
DMA Stream X Memory 1 Address Register (Dma_Sxm1Ar)
224
DMA Stream X FIFO Control Register (Dma_Sxfcr)
225
DMA Register Map
227
Table 39. DMA Register Map and Reset Values
227
Interrupts and Events
231
Nested Vectored Interrupt Controller (NVIC)
231
NVIC Features
231
Systick Calibration Value Register
231
Interrupt and Exception Vectors
231
External Interrupt/Event Controller (EXTI)
231
Table 40. Vector Table for Stm32F412Xx
232
EXTI Main Features
235
EXTI Block Diagram
236
Wakeup Event Management
236
Figure 29. External Interrupt/Event Controller Block Diagram
236
Functional Description
237
External Interrupt/Event Line Mapping
238
Figure 30. External Interrupt/Event GPIO Mapping
238
EXTI Registers
239
Interrupt Mask Register (EXTI_IMR)
239
Event Mask Register (EXTI_EMR)
239
Rising Trigger Selection Register (EXTI_RTSR)
241
Falling Trigger Selection Register (EXTI_FTSR)
242
Software Interrupt Event Register (EXTI_SWIER)
243
Pending Register (EXTI_PR)
244
EXTI Register Map
245
Table 41. External Interrupt/Event Controller Register Map and Reset Values
245
Flexible Static Memory Controller (FSMC)
246
Introduction
246
FSMC Main Features
246
FMC Block Diagram
247
Figure 31. FSMC Block Diagram
247
AHB Interface
248
Supported Memories and Transactions
248
External Device Address Mapping
249
NOR/PSRAM Address Mapping
249
Table 42. NOR/PSRAM Bank Selection
249
Figure 32. FSMC Memory Banks
249
NOR Flash/Psram Controller
250
Table 43. NOR/PSRAM External Memory Address
250
External Memory Interface Signals
251
Table 44. Programmable NOR/PSRAM Access Parameters
251
Table 45. Non-Multiplexed I/O nor Flash Memory
252
Table 46. 16-Bit Multiplexed I/O nor Flash Memory
252
Table 47. Non-Multiplexed I/Os PSRAM/SRAM
252
Supported Memories and Transactions
253
Table 48. 16-Bit Multiplexed I/O PSRAM
253
Table 49. nor Flash/Psram: Example of Supported Memories
254
And Transactions
254
General Timing Rules
255
NOR Flash/Psram Controller Asynchronous Transactions
255
Figure 33. Mode 1 Read Access Waveforms
256
Figure 34. Mode 1 Write Access Waveforms
256
Table 50. Fsmc_Bcrx Bitfields (Mode 1)
257
Table 51. Fsmc_Btrx Bitfields (Mode 1)
257
Figure 35. Mode a Read Access Waveforms
258
Figure 36. Mode a Write Access Waveforms
258
Table 52. Fsmc_Bcrx Bitfields (Mode A)
259
Table 53. Fsmc_Btrx Bitfields (Mode A)
259
Table 54. Fsmc_Bwtrx Bitfields (Mode A)
260
Figure 37. Mode 2 and Mode B Read Access Waveforms
260
Figure 38. Mode 2 Write Access Waveforms
261
Figure 39. Mode B Write Access Waveforms
261
Table 55. Fsmc_Bcrx Bitfields (Mode 2/B)
262
Table 56. Fsmc_Btrx Bitfields (Mode 2/B)
262
Table 57. Fsmc_Bwtrx Bitfields (Mode 2/B)
263
Figure 40. Mode C Read Access Waveforms
263
Table 58. Fsmc_Bcrx Bitfields (Mode C)
264
Figure 41. Mode C Write Access Waveforms
264
Table 59. Fsmc_Btrx Bitfields (Mode C)
265
Table 60. Fsmc_Bwtrx Bitfields (Mode C)
265
Figure 42. Mode D Read Access Waveforms
266
Figure 43. Mode D Write Access Waveforms
266
Table 61. Fsmc_Bcrx Bitfields (Mode D)
267
Table 62. Fsmc_Btrx Bitfields (Mode D)
267
Table 63. Fsmc_Bwtrx Bitfields (Mode D)
268
Figure 44. Muxed Read Access Waveforms
268
Table 64. Fsmc_Bcrx Bitfields (Muxed Mode)
269
Figure 45. Muxed Write Access Waveforms
269
Table 65. Fsmc_Btrx Bitfields (Muxed Mode)
270
Figure 46. Asynchronous Wait During a Read Access Waveforms
271
Synchronous Transactions
272
Figure 47. Asynchronous Wait During a Write Access Waveforms
272
Figure 48. Wait Configuration Waveforms
274
Table 66. Fsmc_Bcrx Bitfields (Synchronous Multiplexed Read Mode)
275
Figure 49. Synchronous Multiplexed Read Mode Waveforms - NOR, PSRAM (CRAM)
275
Table 67. Fsmc_Btrx Bitfields (Synchronous Multiplexed Read Mode)
276
Figure 50. Synchronous Multiplexed Write Mode Waveforms - PSRAM (CRAM)
277
Table 68. Fsmc_Bcrx Bitfields (Synchronous Multiplexed Write Mode)
278
Table 69. Fsmc_Btrx Bitfields (Synchronous Multiplexed Write Mode)
278
NOR/PSRAM Controller Registers
279
FSMC Register Map
286
Table 70. FSMC Register Map and Reset Values
286
Quad-SPI Interface (QUADSPI)
288
Introduction
288
QUADSPI Main Features
288
QUADSPI Functional Description
288
QUADSPI Block Diagram
288
Figure 51. QUADSPI Block Diagram When Dual-Flash Mode Is Disabled
288
QUADSPI Pins
289
Table 71. QUADSPI Pins
289
Figure 52. QUADSPI Block Diagram When Dual-Flash Mode Is Enabled
289
QUADSPI Command Sequence
290
Figure 53. an Example of a Read Command in Quad Mode
290
QUADSPI Signal Interface Protocol Modes
292
Figure 54. an Example of a DDR Command in Quad Mode
293
QUADSPI Indirect Mode
294
QUADSPI Status Flag Polling Mode
296
QUADSPI Memory-Mapped Mode
296
QUADSPI Flash Memory Configuration
297
QUADSPI Delayed Data Sampling
297
QUADSPI Configuration
297
QUADSPI Usage
298
Sending the Instruction Only Once
300
QUADSPI Error Management
300
QUADSPI Busy Bit and Abort Functionality
300
Ncs Behavior
301
Figure 55. Ncs When CKMODE = 0 (T = CLK Period)
301
Figure 56. Ncs When CKMODE = 1 in SDR Mode (T = CLK Period)
301
QUADSPI Interrupts
302
Figure 57. Ncs When CKMODE = 1 in DDR Mode (T = CLK Period)
302
Figure 58. Ncs When CKMODE = 1 with an Abort (T = CLK Period)
302
Table 72. QUADSPI Interrupt Requests
303
QUADSPI Registers
304
QUADSPI Control Register (QUADSPI_CR)
304
QUADSPI Device Configuration Register (QUADSPI_DCR)
307
QUADSPI Status Register (QUADSPI_SR)
308
QUADSPI Flag Clear Register (QUADSPI_FCR)
309
QUADSPI Data Length Register (QUADSPI_DLR)
309
QUADSPI Communication Configuration Register (QUADSPI_CCR)
310
QUADSPI Address Register (QUADSPI_AR)
312
QUADSPI Alternate Bytes Registers (QUADSPI_ABR)
313
QUADSPI Data Register (QUADSPI_DR)
313
QUADSPI Polling Status Mask Register (QUADSPI_PSMKR)
314
QUADSPI Polling Status Match Register (QUADSPI_PSMAR)
314
QUADSPI Polling Interval Register (QUADSPI_PIR)
315
QUADSPI Low-Power Timeout Register (QUADSPI_LPTR)
315
QUADSPI Register Map
316
Table 73. QUADSPI Register Map and Reset Values
316
Analog-To-Digital Converter (ADC)
317
ADC Introduction
317
ADC Main Features
317
ADC Functional Description
317
Figure 59. Single ADC Block Diagram
318
ADC On-Off Control
319
ADC Clock
319
Channel Selection
319
Table 74. ADC Pins
319
Single Conversion Mode
320
Continuous Conversion Mode
320
Timing Diagram
321
Analog Watchdog
321
Figure 60. Timing Diagram
321
Scan Mode
322
Table 75. Analog Watchdog Channel Selection
322
Figure 61. Analog Watchdog's Guarded Area
322
Injected Channel Management
323
Figure 62. Injected Conversion Latency
323
Discontinuous Mode
324
Data Alignment
325
Figure 63. Right Alignment of 12-Bit Data
325
Figure 64. Left Alignment of 12-Bit Data
325
Figure 65. Left Alignment of 6-Bit Data
325
Channel-Wise Programmable Sampling Time
326
Conversion on External Trigger and Trigger Polarity
326
Table 76. Configuring the Trigger Polarity
326
Table 77. External Trigger for Regular Channels
327
Fast Conversion Mode
328
Table 78. External Trigger for Injected Channels
328
Data Management
329
Using the DMA
329
Managing a Sequence of Conversions Without Using the DMA
329
Conversions Without DMA and Without Overrun Detection
330
Temperature Sensor
330
Figure 66. Temperature Sensor and VREFINT Channel Block Diagram
330
Battery Charge Monitoring
331
ADC Interrupts
332
Table 79. ADC Interrupts
332
ADC Registers
333
ADC Status Register (ADC_SR)
333
ADC Control Register 1 (ADC_CR1)
334
ADC Control Register 2 (ADC_CR2)
336
ADC Sample Time Register 1 (ADC_SMPR1)
338
ADC Sample Time Register 2 (ADC_SMPR2)
339
ADC Injected Channel Data Offset Register X (Adc_Jofrx) (X=1
339
ADC Watchdog Higher Threshold Register (ADC_HTR)
339
ADC Watchdog Lower Threshold Register (ADC_LTR)
340
ADC Regular Sequence Register 1 (ADC_SQR1)
340
ADC Regular Sequence Register 2 (ADC_SQR2)
341
ADC Regular Sequence Register 3 (ADC_SQR3)
342
ADC Injected Sequence Register (ADC_JSQR)
343
ADC Injected Data Register X (Adc_Jdrx) (X= 1
343
ADC Regular Data Register (ADC_DR)
344
ADC Common Status Register (ADC_CSR)
344
ADC Common Control Register (ADC_CCR)
345
ADC Register Map
346
Table 80. ADC Global Register Map
346
Table 81. ADC Register Map and Reset Values
346
Table 82. ADC Register Map and Reset Values (Common ADC Registers)
347
Digital Filter for Sigma Delta Modulators (DFSDM)
348
Introduction
348
DFSDM Main Features
349
DFSDM Implementation
350
Table 83. DFSDM1 Implementation
350
DFSDM Functional Description
351
DFSDM Block Diagram
351
Figure 67. Single DFSDM Block Diagram
351
DFSDM Pins and Internal Signals
352
Table 84. DFSDM External Pins
352
Table 85. DFSDM Internal Signals
352
Table 86. DFSDM Triggers Connection
352
DFSDM Reset and Clocks
353
Table 87. DFSDM Break Connection
353
Serial Channel Transceivers
354
Figure 68. Input Channel Pins Redirection
355
Figure 69. Channel Transceiver Timing Diagrams
357
Figure 70. Clock Absence Timing Diagram for SPI
358
Figure 71. Clock Absence Timing Diagram for Manchester Coding
359
Figure 72. First Conversion for Manchester Coding (Manchester Synchronization)
361
Configuring the Input Serial Interface
363
Parallel Data Inputs
363
Figure 73. Dfsdm_Chydatinr Registers Operation Modes and Assignment
364
Channel Selection
365
Digital Filter Configuration
365
Figure 74. Example: Sinc3 Filter Response
366
Integrator Unit
367
Analog Watchdog
367
Table 88. Filter Maximum Output Resolution (Peak Data Values from Filter Output)
367
Table 89. Integrator Maximum Output Resolution
367
Short-Circuit Detector
370
Extreme Detector
370
Data Unit Block
371
Signed Data Format
372
Launching Conversions
372
Continuous and Fast Continuous Modes
373
Request Precedence
373
Power Optimization in Run Mode
374
DFSDM Interrupts
374
Table 90. DFSDM Interrupt Requests
375
DFSDM DMA Transfer
376
DFSDM Channel y Registers (Y=0
376
DFSDM Channel y Configuration Register (Dfsdm_Chycfgr1)
376
DFSDM Channel y Configuration Register (Dfsdm_Chycfgr2)
379
DFSDM Channel y Analog Watchdog and Short-Circuit Detector Register (Dfsdm_Chyawscdr)
379
DFSDM Channel y Watchdog Filter Data Register (Dfsdm_Chywdatr)
380
DFSDM Channel y Data Input Register (Dfsdm_Chydatinr)
381
DFSDM Filter X Module Registers (X=0
382
DFSDM Filter X Control Register 1 (Dfsdm_Fltxcr1)
382
DFSDM Filter X Control Register 2 (Dfsdm_Fltxcr2)
384
DFSDM Filter X Interrupt and Status Register (Dfsdm_Fltxisr)
386
DFSDM Filter X Interrupt Flag Clear Register (Dfsdm_Fltxicr)
387
DFSDM Filter X Injected Channel Group Selection Register (Dfsdm_Fltxjchgr)
388
DFSDM Filter X Control Register (Dfsdm_Fltxfcr)
389
DFSDM Filter X Data Register for Injected Group (Dfsdm_Fltxjdatar)
390
DFSDM Filter X Data Register for the Regular Channel (Dfsdm_Fltxrdatar)
391
DFSDM Filter X Analog Watchdog High Threshold Register (Dfsdm_Fltxawhtr)
391
DFSDM Filter X Analog Watchdog Low Threshold Register
392
(Dfsdm_Fltxawltr)
392
DFSDM Filter X Analog Watchdog Status Register
393
(Dfsdm_Fltxawsr)
393
DFSDM Filter X Analog Watchdog Clear Flag Register
393
(Dfsdm_Fltxawcfr)
393
DFSDM Filter X Extremes Detector Maximum Register
394
(Dfsdm_Fltxexmax)
394
DFSDM Filter X Extremes Detector Minimum Register
394
(Dfsdm_Fltxexmin)
394
DFSDM Filter X Conversion Timer Register (Dfsdm_Fltxcnvtimr)
395
DFSDM Register Map
396
Table 91. DFSDM Register Map and Reset Values
396
True Random Number Generator (RNG)
401
Introduction
401
RNG Main Features
401
RNG Functional Description
402
RNG Block Diagram
402
RNG Internal Signals
402
Table 92. RNG Internal Input/Output Signals
402
Figure 75. RNG Block Diagram
402
Random Number Generation
403
Figure 76. Entropy Source Model
403
RNG Initialization
405
RNG Operation
405
RNG Clocking
406
Error Management
406
RNG Low-Power Usage
407
RNG Interrupts
407
RNG Processing Time
407
Table 93. RNG Interrupt Requests
407
RNG Entropy Source Validation
408
Introduction
408
Validation Conditions
408
Data Collection
408
RNG Registers
409
RNG Control Register (RNG_CR)
409
RNG Status Register (RNG_SR)
410
RNG Data Register (RNG_DR)
411
RNG Register Map
412
Table 94. RNG Register Map and Reset Map
412
Advanced-Control Timers (TIM1&TIM8)
413
TIM1&TIM8 Introduction
413
TIM1&TIM8 Main Features
413
Figure 77. Advanced-Control Timer Block Diagram
414
TIM1&TIM8 Functional Description
415
Time-Base Unit
415
Figure 78. Counter Timing Diagram with Prescaler Division Change from 1 to 2
416
Figure 79. Counter Timing Diagram with Prescaler Division Change from 1 to 4
416
Counter Modes
417
Figure 80. Counter Timing Diagram, Internal Clock Divided by 1
417
Figure 81. Counter Timing Diagram, Internal Clock Divided by 2
418
Figure 82. Counter Timing Diagram, Internal Clock Divided by 4
418
Figure 83. Counter Timing Diagram, Internal Clock Divided by N
418
Figure 84. Counter Timing Diagram, Update Event When ARPE=0
419
Figure 85. Counter Timing Diagram, Update Event When ARPE=1
419
Figure 86. Counter Timing Diagram, Internal Clock Divided by 1
421
Figure 87. Counter Timing Diagram, Internal Clock Divided by 2
421
Figure 88. Counter Timing Diagram, Internal Clock Divided by 4
422
Figure 89. Counter Timing Diagram, Internal Clock Divided by N
422
Figure 90. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
423
Figure 91. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
424
Figure 92. Counter Timing Diagram, Internal Clock Divided by 2
424
Figure 93. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
425
Figure 94. Counter Timing Diagram, Internal Clock Divided by N
425
Repetition Counter
426
Figure 95. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
426
Figure 96. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
426
Figure 97. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
427
Clock Selection
428
Figure 98. Control Circuit in Normal Mode, Internal Clock Divided by 1
428
Figure 99. TI2 External Clock Connection Example
429
Figure 100. Control Circuit in External Clock Mode 1
430
Figure 101. External Trigger Input Block
430
Capture/Compare Channels
431
Figure 102. Control Circuit in External Clock Mode 2
431
Figure 103. Capture/Compare Channel (Example: Channel 1 Input Stage)
432
Figure 104. Capture/Compare Channel 1 Main Circuit
432
Figure 105. Output Stage of Capture/Compare Channel (Channels 1 to 3)
433
Figure 106. Output Stage of Capture/Compare Channel (Channel 4)
433
Input Capture Mode
434
PWM Input Mode
435
Forced Output Mode
435
Figure 107. PWM Input Mode Timing
435
Output Compare Mode
436
PWM Mode
437
Figure 108. Output Compare Mode, Toggle on OC1
437
Figure 109. Edge-Aligned PWM Waveforms (ARR=8)
438
Figure 110. Center-Aligned PWM Waveforms (ARR=8)
439
Complementary Outputs and Dead-Time Insertion
440
Figure 111. Complementary Output with Dead-Time Insertion
441
Figure 112. Dead-Time Waveforms with Delay Greater than the Negative Pulse
441
Figure 113. Dead-Time Waveforms with Delay Greater than the Positive Pulse
441
Using the Break Function
442
Figure 114. Output Behavior in Response to a Break
444
Clearing the Ocxref Signal on an External Event
445
Figure 115. Clearing Timx Ocxref
445
6-Step PWM Generation
446
Figure 116. 6-Step Generation, COM Example (OSSR=1)
446
One-Pulse Mode
447
Figure 117. Example of One Pulse Mode
447
Encoder Interface Mode
448
Table 95. Counting Direction Versus Encoder Signals
449
Figure 118. Example of Counter Operation in Encoder Interface Mode
450
Figure 119. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
450
Timer Input XOR Function
451
Interfacing with Hall Sensors
451
Figure 120. Example of Hall Sensor Interface
452
Timx and External Trigger Synchronization
453
Figure 121. Control Circuit in Reset Mode
453
Figure 122. Control Circuit in Gated Mode
454
Figure 123. Control Circuit in Trigger Mode
455
Timer Synchronization
456
Debug Mode
456
Figure 124. Control Circuit in External Clock Mode 2 + Trigger Mode
456
TIM1&TIM8 Registers
457
TIM1&TIM8 Control Register 1 (Timx_Cr1)
457
TIM1&TIM8 Control Register 2 (Timx_Cr2)
458
TIM1&TIM8 Slave Mode Control Register (Timx_Smcr)
460
TIM1&TIM8 Dma/Interrupt Enable Register (Timx_Dier)
462
Table 96. Timx Internal Trigger Connection
462
TIM1&TIM8 Status Register (Timx_Sr)
464
TIM1&TIM8 Event Generation Register (Timx_Egr)
465
TIM1&TIM8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
467
TIM1&TIM8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
470
TIM1&TIM8 Capture/Compare Enable Register (Timx_Ccer)
471
Table 97. Output Control Bits for Complementary Ocx and Ocxn Channels
474
TIM1&TIM8 Counter (Timx_Cnt)
475
TIM1&TIM8 Prescaler (Timx_Psc)
475
TIM1&TIM8 Auto-Reload Register (Timx_Arr)
475
TIM1&TIM8 Repetition Counter Register (Timx_Rcr)
476
TIM1&TIM8 Capture/Compare Register 1 (Timx_Ccr1)
476
TIM1&TIM8 Capture/Compare Register 2 (Timx_Ccr2)
477
TIM1&TIM8 Capture/Compare Register 3 (Timx_Ccr3)
477
TIM1&TIM8 Capture/Compare Register 4 (Timx_Ccr4)
478
TIM1&TIM8 Break and Dead-Time Register (Timx_Bdtr)
478
TIM1&TIM8 DMA Control Register (Timx_Dcr)
480
TIM1&TIM8 DMA Address for Full Transfer (Timx_Dmar)
481
TIM1&TIM8 Register Map
482
Table 98. TIM1&TIM8 Register Map and Reset Values
482
General-Purpose Timers (TIM2 to TIM5)
484
TIM2 to TIM5 Introduction
484
TIM2 to TIM5 Main Features
484
TIM2 to TIM5 Functional Description
485
Time-Base Unit
485
Figure 125. General-Purpose Timer Block Diagram
485
Figure 126. Counter Timing Diagram with Prescaler Division Change from 1 to 2
486
Counter Modes
487
Figure 127. Counter Timing Diagram with Prescaler Division Change from 1 to 4
487
Figure 128. Counter Timing Diagram, Internal Clock Divided by 1
488
Figure 129. Counter Timing Diagram, Internal Clock Divided by 2
488
Figure 130. Counter Timing Diagram, Internal Clock Divided by 4
488
Figure 131. Counter Timing Diagram, Internal Clock Divided by N
489
Figure 132. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
489
Figure 133. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
490
Figure 134. Counter Timing Diagram, Internal Clock Divided by 1
491
Figure 135. Counter Timing Diagram, Internal Clock Divided by 2
491
Figure 136. Counter Timing Diagram, Internal Clock Divided by 4
491
Figure 137. Counter Timing Diagram, Internal Clock Divided by N
492
Figure 138. Counter Timing Diagram, Update Event
492
Figure 139. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
493
Figure 140. Counter Timing Diagram, Internal Clock Divided by 2
494
Figure 141. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
494
Figure 142. Counter Timing Diagram, Internal Clock Divided by N
494
Figure 143. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
495
Figure 144. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
495
Clock Selection
496
Figure 145. Control Circuit in Normal Mode, Internal Clock Divided by 1
496
Figure 146. TI2 External Clock Connection Example
497
Figure 147. Control Circuit in External Clock Mode 1
498
Figure 148. External Trigger Input Block
498
Capture/Compare Channels
499
Figure 149. Control Circuit in External Clock Mode 2
499
Figure 150. Capture/Compare Channel (Example: Channel 1 Input Stage)
500
Figure 151. Capture/Compare Channel 1 Main Circuit
500
Input Capture Mode
501
Figure 152. Output Stage of Capture/Compare Channel (Channel 1)
501
PWM Input Mode
502
Forced Output Mode
503
Figure 153. PWM Input Mode Timing
503
Output Compare Mode
504
PWM Mode
505
Figure 154. Output Compare Mode, Toggle on OC1
505
Figure 155. Edge-Aligned PWM Waveforms (ARR=8)
506
Figure 156. Center-Aligned PWM Waveforms (ARR=8)
507
One-Pulse Mode
508
Figure 157. Example of One-Pulse Mode
508
Clearing the Ocxref Signal on an External Event
509
Encoder Interface Mode
510
Figure 158. Clearing Timx Ocxref
510
Table 99. Counting Direction Versus Encoder Signals
511
Figure 159. Example of Counter Operation in Encoder Interface Mode
512
Figure 160. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
512
Timer Input XOR Function
513
Timers and External Trigger Synchronization
513
Figure 161. Control Circuit in Reset Mode
513
Figure 162. Control Circuit in Gated Mode
514
Figure 163. Control Circuit in Trigger Mode
515
Timer Synchronization
516
Figure 164. Control Circuit in External Clock Mode 2 + Trigger Mode
516
Figure 165. Master/Slave Timer Example
516
Figure 166. Gating Timer 2 with OC1REF of Timer 1
517
Figure 167. Gating Timer 2 with Enable of Timer 1
518
Figure 168. Triggering Timer 2 with Update of Timer 1
519
Figure 169. Triggering Timer 2 with Enable of Timer 1
520
Debug Mode
521
Figure 170. Triggering Timer 1 and 2 with Timer 1 TI1 Input
521
TIM2 to TIM5 Registers
522
Timx Control Register 1 (Timx_Cr1)
522
Timx Control Register 2 (Timx_Cr2)
524
Timx Slave Mode Control Register (Timx_Smcr)
525
Table 100. Timx Internal Trigger Connections
526
Timx Dma/Interrupt Enable Register (Timx_Dier)
527
Timx Status Register (Timx_Sr)
528
Timx Event Generation Register (Timx_Egr)
530
Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
531
Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
534
Timx Capture/Compare Enable Register (Timx_Ccer)
535
Table 101. Output Control Bit for Standard Ocx Channels
536
Timx Counter (Timx_Cnt)
537
Timx Prescaler (Timx_Psc)
537
Timx Auto-Reload Register (Timx_Arr)
537
Timx Capture/Compare Register 1 (Timx_Ccr1)
538
Timx Capture/Compare Register 2 (Timx_Ccr2)
538
Timx Capture/Compare Register 3 (Timx_Ccr3)
539
Timx Capture/Compare Register 4 (Timx_Ccr4)
539
Timx DMA Control Register (Timx_Dcr)
540
Timx DMA Address for Full Transfer (Timx_Dmar)
540
TIM2 Option Register (TIM2_OR)
541
TIM5 Option Register (TIM5_OR)
542
Timx Register Map
543
Table 102. TIM2 to TIM5 Register Map and Reset Values
543
General-Purpose Timers (TIM9 to TIM14)
545
TIM9 to TIM14 Introduction
545
TIM9 to TIM14 Main Features
545
TIM9/TIM12 Main Features
545
TIM10/TIM11 and TIM13/TIM14 Main Features
546
Figure 171. General-Purpose Timer Block Diagram (TIM9 and TIM12)
546
Figure 172. General-Purpose Timer Block Diagram (TIM10/11/13/14)
547
TIM9 to TIM14 Functional Description
548
Time-Base Unit
548
Figure 173. Counter Timing Diagram with Prescaler Division Change from 1 to 2
549
Figure 174. Counter Timing Diagram with Prescaler Division Change from 1 to 4
549
Counter Modes
550
Figure 175. Counter Timing Diagram, Internal Clock Divided by 1
550
Figure 176. Counter Timing Diagram, Internal Clock Divided by 2
551
Figure 177. Counter Timing Diagram, Internal Clock Divided by 4
551
Figure 178. Counter Timing Diagram, Internal Clock Divided by N
551
Figure 179. Counter Timing Diagram, Update Event When ARPE=0
552
Figure 180. Counter Timing Diagram, Update Event When ARPE=1
552
Clock Selection
553
Figure 181. Control Circuit in Normal Mode, Internal Clock Divided by 1
553
Figure 182. TI2 External Clock Connection Example
554
Figure 183. Control Circuit in External Clock Mode 1
554
Capture/Compare Channels
555
Figure 184. Capture/Compare Channel (Example: Channel 1 Input Stage)
555
Input Capture Mode
556
Figure 185. Capture/Compare Channel 1 Main Circuit
556
Figure 186. Output Stage of Capture/Compare Channel (Channel 1)
556
PWM Input Mode (Only for TIM9/12)
557
Forced Output Mode
558
Figure 187. PWM Input Mode Timing
558
Output Compare Mode
559
PWM Mode
560
Figure 188. Output Compare Mode, Toggle on OC1
560
One-Pulse Mode
561
Figure 189. Edge-Aligned PWM Waveforms (ARR=8)
561
Figure 190. Example of One Pulse Mode
562
TIM9/12 External Trigger Synchronization
563
Figure 191. Control Circuit in Reset Mode
564
Figure 192. Control Circuit in Gated Mode
565
Figure 193. Control Circuit in Trigger Mode
565
Timer Synchronization (TIM9/12)
566
Debug Mode
566
TIM9 and TIM12 Registers
566
TIM9/12 Control Register 1 (Timx_Cr1)
566
TIM9/12 Slave Mode Control Register (Timx_Smcr)
568
TIM9/12 Interrupt Enable Register (Timx_Dier)
569
Table 103. Timx Internal Trigger Connections
569
TIM9/12 Status Register (Timx_Sr)
570
TIM9/12 Event Generation Register (Timx_Egr)
572
TIM9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)
572
TIM9/12 Capture/Compare Enable Register (Timx_Ccer)
576
TIM9/12 Counter (Timx_Cnt)
577
TIM9/12 Prescaler (Timx_Psc)
577
TIM9/12 Auto-Reload Register (Timx_Arr)
577
Table 104. Output Control Bit for Standard Ocx Channels
577
TIM9/12 Capture/Compare Register 1 (Timx_Ccr1)
578
TIM9/12 Capture/Compare Register 2 (Timx_Ccr2)
578
TIM9/12 Register Map
579
Table 105. TIM9/12 Register Map and Reset Values
579
TIM10/11/13/14 Registers
581
TIM10/11/13/14 Control Register 1 (Timx_Cr1)
581
TIM10/11/13/14 Interrupt Enable Register (Timx_Dier)
582
TIM10/11/13/14 Status Register (Timx_Sr)
582
TIM10/11/13/14 Event Generation Register (Timx_Egr)
583
TIM10/11/13/14 Capture/Compare Mode Register 1
584
(Timx_Ccmr1)
584
TIM10/11/13/14 Capture/Compare Enable Register
587
(Timx_Ccer)
587
Table 106. Output Control Bit for Standard Ocx Channels
587
TIM10/11/13/14 Counter (Timx_Cnt)
588
TIM10/11/13/14 Prescaler (Timx_Psc)
588
TIM10/11/13/14 Auto-Reload Register (Timx_Arr)
588
TIM10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)
589
TIM11 Option Register 1 (TIM11_OR)
589
TIM10/11/13/14 Register Map
590
Table 107. TIM10/11/13/14 Register Map and Reset Values
590
Basic Timers (TIM6/7)
592
Introduction
592
TIM6/7 Main Features
592
Figure 194. Basic Timer Block Diagram
592
TIM6/7 Functional Description
593
Time-Base Unit
593
Figure 195. Counter Timing Diagram with Prescaler Division Change from 1 to 2
594
Figure 196. Counter Timing Diagram with Prescaler Division Change from 1 to 4
594
Counting Mode
595
Figure 197. Counter Timing Diagram, Internal Clock Divided by 1
595
Figure 198. Counter Timing Diagram, Internal Clock Divided by 2
596
Figure 199. Counter Timing Diagram, Internal Clock Divided by 4
596
Figure 200. Counter Timing Diagram, Internal Clock Divided by N
597
Clock Source
598
Debug Mode
599
Figure 203. Control Circuit in Normal Mode, Internal Clock Divided by 1
599
TIM6/7 Registers
600
TIM6/7 Control Register 1 (Timx_Cr1)
600
TIM6/7 Control Register 2 (Timx_Cr2)
601
TIM6/7 Dma/Interrupt Enable Register (Timx_Dier)
601
TIM6/7 Status Register (Timx_Sr)
602
TIM6/7 Event Generation Register (Timx_Egr)
602
TIM6/7 Counter (Timx_Cnt)
602
TIM6/7 Prescaler (Timx_Psc)
603
TIM6/7 Auto-Reload Register (Timx_Arr)
603
TIM6/7 Register Map
604
Table 108. TIM6/7 Register Map and Reset Values
604
Independent Watchdog (IWDG)
605
IWDG Introduction
605
IWDG Main Features
605
IWDG Functional Description
605
Hardware Watchdog
605
Register Access Protection
605
Debug Mode
606
Table 109. Min/Max IWDG Timeout Period at 32 Khz (LSI)
606
Figure 204. Independent Watchdog Block Diagram
606
IWDG Registers
607
Key Register (IWDG_KR)
607
Prescaler Register (IWDG_PR)
608
Reload Register (IWDG_RLR)
609
Status Register (IWDG_SR)
609
IWDG Register Map
610
Table 110. IWDG Register Map and Reset Values
610
Window Watchdog (WWDG)
611
WWDG Introduction
611
WWDG Main Features
611
WWDG Functional Description
611
Figure 205. Watchdog Block Diagram
612
How to Program the Watchdog Timeout
613
Figure 206. Window Watchdog Timing Diagram
613
Debug Mode
614
WWDG Registers
615
Control Register (WWDG_CR)
615
Configuration Register (WWDG_CFR)
616
Status Register (WWDG_SR)
616
WWDG Register Map
617
Table 111. WWDG Register Map and Reset Values
617
Real-Time Clock (RTC)
618
Introduction
618
RTC Main Features
618
RTC Functional Description
620
Clock and Prescalers
620
Real-Time Clock and Calendar
620
Figure 207. RTC Block Diagram
620
Programmable Alarms
621
Periodic Auto-Wakeup
621
RTC Initialization and Configuration
622
Reading the Calendar
624
Resetting the RTC
625
RTC Synchronization
625
RTC Reference Clock Detection
626
RTC Coarse Digital Calibration
626
RTC Smooth Digital Calibration
627
Timestamp Function
629
Tamper Detection
630
Calibration Clock Output
631
Alarm Output
632
RTC and Low Power Modes
632
Table 112. Effect of Low Power Modes on RTC
632
RTC Interrupts
633
Table 113. Interrupt Control Bits
633
RTC Registers
634
RTC Time Register (RTC_TR)
634
RTC Date Register (RTC_DR)
635
RTC Control Register (RTC_CR)
636
RTC Initialization and Status Register (RTC_ISR)
638
RTC Prescaler Register (RTC_PRER)
640
RTC Wakeup Timer Register (RTC_WUTR)
641
RTC Calibration Register (RTC_CALIBR)
641
RTC Alarm a Register (RTC_ALRMAR)
643
RTC Alarm B Register (RTC_ALRMBR)
644
RTC Write Protection Register (RTC_WPR)
645
RTC Sub Second Register (RTC_SSR)
645
RTC Shift Control Register (RTC_SHIFTR)
646
RTC Time Stamp Time Register (RTC_TSTR)
647
RTC Time Stamp Date Register (RTC_TSDR)
647
RTC Timestamp Sub Second Register (RTC_TSSSR)
648
RTC Calibration Register (RTC_CALR)
648
RTC Tamper and Alternate Function Configuration Register
649
(Rtc_Tafcr)
649
RTC Alarm a Sub Second Register (RTC_ALRMASSR)
651
RTC Alarm B Sub Second Register (RTC_ALRMBSSR)
652
RTC Backup Registers (Rtc_Bkpxr)
653
RTC Register Map
653
Table 114. RTC Register Map and Reset Values
653
Fast-Mode Plus Inter-Integrated Circuit (FMPI2C) Interface
656
Introduction
656
FMPI2C Main Features
656
FMPI2C Implementation
657
FMPI2C Functional Description
657
Table 115. Stm32F412Xx FMPI2C Implementation
657
FMPI2C Block Diagram
658
Figure 208. FMPI2C Block Diagram
658
FMPI2C Pins and Internal Signals
659
FMPI2C Clock Requirements
659
Table 116. FMPI2C Input/Output Pins
659
Table 117. FMPI2C Internal Input/Output Signals
659
Mode Selection
660
FMPI2C Initialization
660
Figure 209. I2C Bus Protocol
660
Table 118. Comparison of Analog Vs. Digital Filters
661
Figure 210. Setup and Hold Timings
662
Table 119. I2C-Smbus Specification Data Setup and Hold Times
663
Software Reset
665
Figure 211. FMPI2C Initialization Flowchart
665
Data Transfer
666
Figure 212. Data Reception
666
Figure 213. Data Transmission
667
FMPI2C Slave Mode
668
Table 120. FMPI2C Configuration
668
Figure 214. Slave Initialization Flowchart
670
Figure 215. Transfer Sequence Flowchart for FMPI2C Slave Transmitter
672
Figure 216. Transfer Sequence Flowchart for FMPI2C Slave Transmitter
673
Figure 217. Transfer Bus Diagrams for FMPI2C Slave Transmitter
674
Figure 218. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=0
675
Figure 219. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=1
676
Figure 220. Transfer Bus Diagrams for FMPI2C Slave Receiver
676
FMPI2C Master Mode
677
Figure 221. Master Clock Generation
678
Table 121. I2C-Smbus Specification Clock Timings
679
Figure 222. Master Initialization Flowchart
680
Figure 223. 10-Bit Address Read Access with HEAD10R=0
680
Figure 224. 10-Bit Address Read Access with HEAD10R=1
681
Figure 225. Transfer Sequence Flowchart for FMPI2C Master Transmitter for N≤255 Bytes
682
Figure 226. Transfer Sequence Flowchart for FMPI2C Master Transmitter for N>255 Bytes
683
Figure 227. Transfer Bus Diagrams for FMPI2C Master Transmitter
684
Figure 228. Transfer Sequence Flowchart for FMPI2C Master Receiver for N≤255 Bytes
686
Figure 229. Transfer Sequence Flowchart for FMPI2C Master Receiver for N >255 Bytes
687
Figure 230. Transfer Bus Diagrams for FMPI2C Master Receiver
688
FMPI2C_TIMINGR Register Configuration Examples
689
Table 122. Examples of Timing Settings for Fi2Cclk = 8 Mhz
689
Table 123. Examples of Timings Settings for Fi2Cclk = 16 Mhz
689
Smbus Specific Features
690
Table 124. Smbus Timeout Specifications
692
Figure 231. Timeout Intervals for T
692
Smbus Initialization
693
Table 125. Smbus with PEC Configuration
694
Table 126. Examples of TIMEOUTA Settings for Various FMPI2CCLK Frequencies
694
Smbus: FMPI2C_TIMEOUTR Register Configuration Examples
695
Smbus Slave Mode
695
Table 127. Examples of TIMEOUTB Settings for Various FMPI2CCLK Frequencies
695
Table 128. Examples of TIMEOUTA Settings for Various FMPI2CCLK Frequencies (Max T IDLE = 50 Μs)
695
Figure 232. Transfer Sequence Flowchart for Smbus Slave Transmitter N Bytes + PEC
696
Figure 233. Transfer Bus Diagrams for Smbus Slave Transmitter (SBC=1)
697
Figure 234. Transfer Sequence Flowchart for Smbus Slave Receiver N Bytes + PEC
698
Figure 235. Bus Transfer Diagrams for Smbus Slave Receiver (SBC=1)
699
Figure 236. Bus Transfer Diagrams for Smbus Master Transmitter
700
Error Conditions
702
Figure 237. Bus Transfer Diagrams for Smbus Master Receiver
702
DMA Requests
704
Debug Mode
705
FMPI2C Low-Power Modes
705
Table 129. Effect of Low-Power Modes on the FMPI2C
705
FMPI2C Interrupts
706
Table 130. FMPI2C Interrupt Requests
706
FMPI2C Registers
707
FMPI2C Control Register 1 (FMPI2C_CR1)
707
FMPI2C Control Register 2 (FMPI2C_CR2)
709
FMPI2C Own Address 1 Register (FMPI2C_OAR1)
712
FMPI2C Own Address 2 Register (FMPI2C_OAR2)
713
FMPI2C Timing Register (FMPI2C_TIMINGR)
714
FMPI2C Timeout Register (FMPI2C_TIMEOUTR)
715
FMPI2C Interrupt and Status Register (FMPI2C_ISR)
716
FMPI2C Interrupt Clear Register (FMPI2C_ICR)
718
FMPI2C PEC Register (FMPI2C_PECR)
719
FMPI2C Receive Data Register (FMPI2C_RXDR)
720
FMPI2C Transmit Data Register (FMPI2C_TXDR)
720
FMPI2C Register Map
721
Table 131. FMPI2C Register Map and Reset Values
721
Inter-Integrated Circuit
723
C Introduction
723
I 2 C Main Features
724
C Functional Description
725
Mode Selection
725
Figure 238. I2C Bus Protocol
725
I2C Slave Mode
726
Figure 239. I2C Block Diagram
726
Figure 240. Transfer Sequence Diagram for Slave Transmitter
728
I2C Master Mode
729
Figure 241. Transfer Sequence Diagram for Slave Receiver
729
Figure 242. Transfer Sequence Diagram for Master Transmitter
732
Figure 243. Transfer Sequence Diagram for Master Receiver
734
Error Conditions
735
Programmable Noise Filter
736
Table 132. Maximum DNF[3:0] Value to be Compliant with Thd:dat(Max)
736
SDA/SCL Line Control
737
Smbus
737
Table 133. Smbus Vs. I2C
738
DMA Requests
740
Packet Error Checking
741
I 2 C Interrupts
742
Table 134. I2C Interrupt Requests
742
Figure 244. I2C Interrupt Mapping Diagram
743
I 2 C Debug Mode
744
I 2 C Registers
744
I 2 C Control Register 1 (I2C_CR1)
744
I 2 C Control Register 2 (I2C_CR2)
746
I 2 C Own Address Register 1 (I2C_OAR1)
748
I 2 C Own Address Register 2 (I2C_OAR2)
748
C Data Register (I2C_DR)
749
C Status Register 1 (I2C_SR1)
749
I 2 C Status Register 2 (I2C_SR2)
753
I 2 C Clock Control Register (I2C_CCR)
754
I 2 C TRISE Register (I2C_TRISE)
755
C FLTR Register (I2C_FLTR)
756
I2C Register Map
757
Table 135. I2C Register Map and Reset Values
757
Universal Synchronous Receiver Transmitter (USART) /Universal Asynchronous Receiver Transmitter (UART)
758
USART Introduction
758
USART Main Features
759
USART Implementation
760
USART Functional Description
760
Table 136. USART Features
760
Figure 245. USART Block Diagram
762
USART Character Description
763
Figure 246. Word Length Programming
763
Transmitter
764
Figure 247. Configurable Stop Bits
765
Figure 248. TC/TXE Behavior When Transmitting
766
Receiver
767
Figure 249. Start Bit Detection When Oversampling by 16 or 8
767
Figure 250. Data Sampling When Oversampling by 16
770
Table 137. Noise Detection from Sampled Data
771
Figure 251. Data Sampling When Oversampling by 8
771
Fractional Baud Rate Generation
772
Table 138. Error Calculation for Programmed Baud Rates at F
774
USART Receiver Tolerance to Clock Deviation
782
Multiprocessor Communication
783
Table 150. USART Receiver Tolerance When DIV Fraction Is 0
783
Table 151. USART Receiver Tolerance When Div_Fraction Is Different from 0
783
Figure 252. Mute Mode Using Idle Line Detection
784
Parity Control
785
Table 152. Frame Formats
785
Figure 253. Mute Mode Using Address Mark Detection
785
LIN (Local Interconnection Network) Mode
786
Figure 254. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)
787
USART Synchronous Mode
788
Figure 255. Break Detection in LIN Mode Vs. Framing Error Detection
788
Figure 256. USART Example of Synchronous Transmission
789
Figure 257. USART Data Clock Timing Diagram (M=0)
789
Single-Wire Half-Duplex Communication
790
Figure 258. USART Data Clock Timing Diagram (M=1)
790
Figure 259. RX Data Setup/Hold Time
790
Smartcard
791
Figure 260. ISO 7816-3 Asynchronous Protocol
791
Figure 261. Parity Error Detection Using the 1.5 Stop Bits
792
Irda SIR ENDEC Block
793
Figure 262. Irda SIR ENDEC- Block Diagram
794
Figure 263. Irda Data Modulation (3/16) -Normal Mode
794
Continuous Communication Using DMA
795
Figure 264. Transmission Using DMA
796
Hardware Flow Control
797
Figure 265. Reception Using DMA
797
Figure 266. Hardware Flow Control between 2 Usarts
797
Figure 267. RTS Flow Control
798
Figure 268. CTS Flow Control
798
USART Interrupts
799
Table 153. USART Interrupt Requests
799
USART Registers
800
Status Register (USART_SR)
800
Figure 269. USART Interrupt Mapping Diagram
800
Data Register (USART_DR)
803
Baud Rate Register (USART_BRR)
803
Control Register 1 (USART_CR1)
804
Control Register 2 (USART_CR2)
806
Control Register 3 (USART_CR3)
807
Guard Time and Prescaler Register (USART_GTPR)
809
USART Register Map
810
Table 154. USART Register Map and Reset Values
810
Serial Peripheral Interface/ Inter-IC Sound (SPI/I2S)
811
Introduction
811
SPI Main Features
812
SPI Extended Features
813
I2S Features
813
SPI/I2S Implementation
813
Table 155. Stm32F412Xx SPI Implementation
813
SPI Functional Description
814
General Description
814
Figure 270. SPI Block Diagram
814
Communications between One Master and One Slave
815
Figure 271. Full-Duplex Single Master/ Single Slave Application
815
Figure 272. Half-Duplex Single Master/ Single Slave Application
816
Figure 273. Simplex Single Master/Single Slave Application
817
Standard Multi-Slave Communication
818
Figure 274. Master and Three Independent Slaves
818
Multi-Master Communication
819
Slave Select (NSS) Pin Management
819
Figure 275. Multi-Master Application
819
Figure 276. Hardware/Software Slave Select Management
820
Communication Formats
821
Figure 277. Data Clock Timing Diagram
822
SPI Configuration
823
Procedure for Enabling SPI
823
Data Transmission and Reception Procedures
824
Figure 278. TXE/RXNE/BSY Behavior in Master / Full-Duplex Mode (BIDIMODE=0, RXONLY=0) in the Case of Continuous Transfers
825
Procedure for Disabling the SPI
826
Figure 279. TXE/RXNE/BSY Behavior in Slave / Full-Duplex Mode (BIDIMODE=0, RXONLY=0) in the Case of Continuous Transfers
826
Communication Using DMA (Direct Memory Addressing)
827
Figure 280. Transmission Using DMA
828
SPI Status Flags
829
Figure 281. Reception Using DMA
829
SPI Error Flags
830
SPI Special Features
831
TI Mode
831
CRC Calculation
832
Figure 282. TI Mode Transfer
832
SPI Interrupts
834
Table 156. SPI Interrupt Requests
834
S Functional Description
835
S General Description
835
Figure 283. I
835
I2S Full-Duplex
836
Figure 284. I2S Full-Duplex Block Diagram
836
Supported Audio Protocols
837
Figure 285. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy, CPOL = 0)
838
Figure 286. I 2 S Philips Standard Waveforms (24-Bit Frame with CPOL = 0)
838
Figure 287. Transmitting 0X8Eaa33
838
Figure 288. Receiving 0X8Eaa33
839
Figure 289. I
839
Figure 290. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame
839
Figure 291. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length with CPOL = 0
840
Figure 292. MSB Justified 24-Bit Frame Length with CPOL = 0
840
Figure 293. MSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
840
Figure 294. LSB Justified 16-Bit or 32-Bit Full-Accuracy with CPOL = 0
841
Figure 295. LSB Justified 24-Bit Frame Length with CPOL = 0
841
Figure 296. Operations Required to Transmit 0X3478Ae
841
Figure 297. Operations Required to Receive 0X3478Ae
842
Figure 298. LSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
842
Figure 299. Example of 16-Bit Data Frame Extended to 32-Bit Channel Frame
842
Clock Generator
843
Figure 300. PCM Standard Waveforms (16-Bit)
843
Figure 301. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)
843
Figure 302. Audio Sampling Frequency Definition
844
Figure 303. I
844
Table 157. Audio-Frequency Precision Using Standard 8 Mhz HSE
845
I 2 S Master Mode
846
I 2 S Slave Mode
848
I 2 S Status Flags
849
I 2 S Error Flags
850
I 2 S Interrupts
851
DMA Features
851
Table 158. I
851
SPI and I 2 S Registers
852
SPI Control Register 1 (SPI_CR1) (Not Used in I 2 S Mode)
852
SPI Control Register 2 (SPI_CR2)
854
SPI Status Register (SPI_SR)
855
SPI Data Register (SPI_DR)
857
SPI CRC Polynomial Register (SPI_CRCPR) (Not Used in I
857
Mode
857
SPI RX CRC Register (SPI_RXCRCR) (Not Used in I 2 S Mode)
858
SPI TX CRC Register (SPI_TXCRCR) (Not Used in I 2 S Mode)
858
SPI_I 2 S Configuration Register (SPI_I2SCFGR)
859
SPI_I 2 S Prescaler Register (SPI_I2SPR)
860
SPI Register Map
862
Table 159. SPI Register Map and Reset Values
862
Secure Digital Input/Output Interface (SDIO)
863
SDIO Main Features
863
SDIO Bus Topology
863
Figure 304. "No Response" and "No Data" Operations
864
Figure 305. (Multiple) Block Read Operation
864
Figure 306. (Multiple) Block Write Operation
864
SDIO Functional Description
865
Figure 307. Sequential Read Operation
865
Figure 308. Sequential Write Operation
865
Figure 309. SDIO Block Diagram
865
Table 160. SDIO I/O Definitions
866
SDIO Adapter
867
Figure 310. SDIO Adapter
867
Figure 311. Control Unit
868
Figure 312. SDIO_CK Clock Dephasing (BYPASS = 0)
868
Figure 313. SDIO Adapter Command Path
869
Figure 314. Command Path State Machine (SDIO)
870
Table 161. Command Format
871
Figure 315. SDIO Command Transfer
871
Table 162. Short Response Format
872
Table 163. Long Response Format
872
Table 164. Command Path Status Flags
872
Figure 316. Data Path
873
Figure 317. Data Path State Machine (DPSM)
874
Table 165. Data Token Format
875
Table 166. DPSM Flags
876
Table 167. Transmit FIFO Status Flags
877
Table 168. Receive FIFO Status Flags
877
SDIO APB2 Interface
878
Card Functional Description
879
Card Identification Mode
879
Card Reset
880
Operating Voltage Range Validation
880
Card Identification Process
880
Block Write
881
Block Read
882
Stream Access, Stream Write and Stream Read (Multimediacard Only)
882
Erase: Group Erase and Sector Erase
884
Wide Bus Selection or Deselection
884
Protection Management
884
Card Status Register
888
Table 169. Card Status
888
SD Status Register
891
Table 170. SD Status
891
Table 171. Speed Class Code Field
892
Table 172. Performance Move Field
893
Table 173. AU_SIZE Field
893
Table 174. Maximum AU Size
893
Table 175. Erase Size Field
894
Table 176. Erase Timeout Field
894
Table 177. Erase Offset Field
894
SD I/O Mode
895
Commands and Responses
896
Table 178. Block-Oriented Write Commands
897
Table 179. Block-Oriented Write Protection Commands
898
Table 180. Erase Commands
898
Table 181. I/O Mode Commands
898
Response Formats
899
Table 182. Lock Card
899
Table 183. Application-Specific Commands
899
R1 (Normal Response Command)
900
R1B
900
R2 (CID, CSD Register)
900
Table 184. R1 Response
900
Table 185. R2 Response
900
R3 (OCR Register)
901
R4 (Fast I/O)
901
R4B
901
Table 186. R3 Response
901
Table 187. R4 Response
901
Table 188. R4B Response
901
R5 (Interrupt Request)
902
Table 189. R5 Response
902
SDIO I/O Card-Specific Operations
903
SDIO I/O Read Wait Operation by SDIO_D2 Signalling
903
Table 190. R6 Response
903
SDIO Read Wait Operation by Stopping SDIO_CK
904
SDIO Suspend/Resume Operation
904
SDIO Interrupts
904
HW Flow Control
904
SDIO Registers
905
SDIO Power Control Register (SDIO_POWER)
905
SDIO Clock Control Register (SDIO_CLKCR)
905
SDIO Argument Register (SDIO_ARG)
907
SDIO Command Register (SDIO_CMD)
907
SDIO Command Response Register (SDIO_RESPCMD)
908
SDIO Response 1
908
SDIO Data Timer Register (SDIO_DTIMER)
909
Table 191. Response Type and Sdio_Respx Registers
909
SDIO Data Length Register (SDIO_DLEN)
910
SDIO Data Control Register (SDIO_DCTRL)
910
SDIO Data Counter Register (SDIO_DCOUNT)
913
SDIO Status Register (SDIO_STA)
913
SDIO Interrupt Clear Register (SDIO_ICR)
914
SDIO Mask Register (SDIO_MASK)
916
SDIO FIFO Counter Register (SDIO_FIFOCNT)
918
SDIO Data FIFO Register (SDIO_FIFO)
919
SDIO Register Map
920
Table 192. SDIO Register Map
920
Controller Area Network (Bxcan)
922
Introduction
922
Bxcan Main Features
922
Bxcan General Description
923
CAN 2.0B Active Core
923
Control, Status and Configuration Registers
923
Tx Mailboxes
923
Figure 318. CAN Network Topology
923
Acceptance Filters
924
Figure 319. Dual-CAN Block Diagram
924
Bxcan Operating Modes
925
Initialization Mode
925
Normal Mode
925
Sleep Mode (Low-Power)
926
Figure 320. Bxcan Operating Modes
926
Test Mode
927
Silent Mode
927
Loop Back Mode
927
Figure 321. Bxcan in Silent Mode
927
Figure 322. Bxcan in Loop Back Mode
927
Loop Back Combined with Silent Mode
928
Behavior in Debug Mode
928
Bxcan Functional Description
928
Transmission Handling
928
Figure 323. Bxcan in Combined Mode
928
Time Triggered Communication Mode
930
Reception Handling
930
Figure 324. Transmit Mailbox States
930
Figure 325. Receive FIFO States
931
Identifier Filtering
932
Figure 326. Filter Bank Scale Configuration - Register Organization
934
Figure 327. Example of Filter Numbering
935
Message Storage
936
Figure 328. Filtering Mechanism - Example
936
Table 193. Transmit Mailbox Mapping
937
Table 194. Receive Mailbox Mapping
937
Figure 329. CAN Error State Diagram
937
Error Management
938
Bit Timing
938
Figure 330. Bit Timing
939
Figure 331. CAN Frames
940
Bxcan Interrupts
941
Figure 332. Event Flags and Interrupt Generation
941
CAN Registers
942
Register Access Protection
942
CAN Control and Status Registers
942
CAN Mailbox Registers
952
Figure 333. CAN Mailbox Registers
952
CAN Filter Registers
959
Bxcan Register Map
963
Table 195. Bxcan Register Map and Reset Values
963
USB On-The-Go Full-Speed (OTG_FS)
967
Introduction
967
Table 196. OTG_FS Speeds Supported
967
OTG_FS Main Features
968
General Features
968
Host-Mode Features
969
Peripheral-Mode Features
969
Split Rail for USB
969
OTG_FS Implementation
970
Table 197. OTG_FS Implementation
970
OTG_FS Functional Description
971
OTG_FS Block Diagram
971
OTG_FS Pin and Internal Signals
971
Table 198. OTG_FS Input/Output Pins
971
Figure 334. OTG_FS Full-Speed Block Diagram
971
OTG_FS Core
972
Embedded Full-Speed OTG PHY Connected to OTG_FS
972
Table 199. OTG_FS Input/Output Signals
972
OTG Detections
973
OTG_FS Dual Role Device (DRD)
973
ID Line Detection
973
Figure 335. OTG_FS A-B Device Connection
973
HNP Dual Role Device
974
SRP Dual Role Device
974
OTG_FS as a USB Peripheral
974
SRP-Capable Peripheral
975
Peripheral States
975
Figure 336. OTG_FS Peripheral-Only Connection
975
Peripheral Endpoints
976
OTG_FS as a USB Host
978
SRP-Capable Host
979
USB Host States
979
Figure 337. OTG_FS Host-Only Connection
979
Host Channels
981
Host Scheduler
982
OTG_FS SOF Trigger
983
Host Sofs
983
Peripheral Sofs
983
Figure 338. SOF Connectivity (SOF Trigger Output to TIM and ITR1 Connection)
983
OTG_FS Low-Power Modes
984
Table 200. Compatibility of STM32 Low Power Modes with the OTG
984
OTG_FS Dynamic Update of the OTG_HFIR Register
985
OTG_FS Data Fifos
985
Figure 339. Updating OTG_HFIR Dynamically (RLDCTRL = 1)
985
Peripheral FIFO Architecture
986
Figure 340. Device-Mode FIFO Address Mapping and AHB FIFO Access Mapping
986
Host FIFO Architecture
987
Figure 341. Host-Mode FIFO Address Mapping and AHB FIFO Access Mapping
987
FIFO RAM Allocation
988
OTG_FS System Performance
990
OTG_FS Interrupts
990
Figure 342. Interrupt Hierarchy
991
OTG_FS Control and Status Registers
992
CSR Memory Map
992
Table 201. Core Global Control and Status Registers (Csrs)
992
Table 202. Host-Mode Control and Status Registers (Csrs)
993
Table 203. Device-Mode Control and Status Registers
994
OTG_FS Registers
996
Table 204. Data FIFO (DFIFO) Access Register Map
996
Table 205. Power and Clock Gating Control and Status Registers
996
OTG Control and Status Register (OTG_GOTGCTL)
997
OTG Interrupt Register (OTG_GOTGINT)
1000
OTG AHB Configuration Register (OTG_GAHBCFG)
1001
OTG USB Configuration Register (OTG_GUSBCFG)
1002
Table 206. TRDT Values (FS)
1003
OTG Reset Register (OTG_GRSTCTL)
1004
OTG Core Interrupt Register (OTG_GINTSTS)
1006
OTG Interrupt Mask Register (OTG_GINTMSK)
1010
OTG Receive Status Debug Read Register (OTG_GRXSTSR)
1013
OTG Receive Status Debug Read [Alternate] (OTG_GRXSTSR)
1014
OTG Status Read and Pop Registers (OTG_GRXSTSP)
1015
OTG Status Read and Pop Registers [Alternate] (OTG_GRXSTSP)
1016
OTG Receive FIFO Size Register (OTG_GRXFSIZ)
1017
OTG Host Non-Periodic Transmit FIFO Size Register (Otg_Hnptxfsiz)/Endpoint 0 Transmit FIFO Size
1017
(Otg_Dieptxf0)
1017
29.15.14 OTG Non-Periodic Transmit Fifo/Queue Status Register
1018
(Otg_Hnptxsts)
1018
OTG General Core Configuration Register (OTG_GCCFG)
1019
OTG Core ID Register (OTG_CID)
1021
OTG Core LPM Configuration Register (OTG_GLPMCFG)
1021
29.15.18 OTG Host Periodic Transmit FIFO Size Register
1025
(Otg_Hptxfsiz)
1025
29.15.19 OTG Device in Endpoint Transmit FIFO X Size Register
1025
(Otg_Dieptxfx)
1025
29.15.20 Host-Mode Registers
1026
OTG Host Configuration Register (OTG_HCFG)
1026
OTG Host Frame Interval Register (OTG_HFIR)
1027
29.15.23 OTG Host Frame Number/Frame Time Remaining Register
1028
(Otg_Hfnum)
1028
29.15.24 Otg_Host Periodic Transmit Fifo/Queue Status Register
1028
(Otg_Hptxsts)
1028
OTG Host All Channels Interrupt Register (OTG_HAINT)
1029
29.15.26 OTG Host All Channels Interrupt Mask Register
1030
(Otg_Haintmsk)
1030
OTG Host Port Control and Status Register (OTG_HPRT)
1031
OTG Host Channel X Characteristics Register (Otg_Hccharx)
1033
OTG Host Channel X Interrupt Register (Otg_Hcintx)
1034
OTG Host Channel X Interrupt Mask Register (Otg_Hcintmskx)
1035
OTG Host Channel X Transfer Size Register (Otg_Hctsizx)
1036
29.15.32 Device-Mode Registers
1037
OTG Device Configuration Register (OTG_DCFG)
1037
OTG Device Control Register (OTG_DCTL)
1038
Table 207. Minimum Duration for Soft Disconnect
1040
OTG Device Status Register (OTG_DSTS)
1041
29.15.36 OTG Device in Endpoint Common Interrupt Mask Register
1042
(Otg_Diepmsk)
1042
29.15.37 OTG Device out Endpoint Common Interrupt Mask Register
1043
(Otg_Doepmsk)
1043
OTG Device All Endpoints Interrupt Register (OTG_DAINT)
1044
29.15.39 OTG All Endpoints Interrupt Mask Register
1045
(Otg_Daintmsk)
1045
OTG Device
1045
(Otg_Dvbusdis)
1045
BUS Discharge Time Register
1046
OTG Device
1046
(Otg_Dvbuspulse)
1046
BUS Pulsing Time Register
1046
29.15.42 OTG Device in Endpoint FIFO Empty Interrupt Mask Register
1046
(Otg_Diepempmsk)
1046
29.15.43 OTG Device Control in Endpoint 0 Control Register
1047
(Otg_Diepctl0)
1047
OTG Device in Endpoint X Control Register (Otg_Diepctlx)
1048
OTG Device in Endpoint X Interrupt Register (Otg_Diepintx)
1051
29.15.46 OTG Device in Endpoint 0 Transfer Size Register
1052
(Otg_Dieptsiz0)
1052
29.15.47 OTG Device in Endpoint Transmit FIFO Status Register
1053
(Otg_Dtxfstsx)
1053
OTG Device in Endpoint X Transfer Size Register (Otg_Dieptsizx)
1054
29.15.49 OTG Device Control out Endpoint 0 Control Register
1055
(Otg_Doepctl0)
1055
OTG Device out Endpoint X Interrupt Register (Otg_Doepintx)
1056
29.15.51 OTG Device out Endpoint 0 Transfer Size Register
1058
(Otg_Doeptsiz0)
1058
(Otg_Doepctlx)
1059
(Otg_Doeptsizx)
1061
OTG Power and Clock Gating Control Register (OTG_PCGCCTL)
1062
29.15.55 OTG_FS Register Map
1063
Table 208. OTG_FS Register Map and Reset Values
1063
OTG_FS Programming Model
1071
Core Initialization
1071
Host Initialization
1072
Device Initialization
1072
Host Programming Model
1073
Figure 343. Transmit FIFO Write Task
1074
Figure 344. Receive FIFO Read Task
1075
Figure 345. Normal Bulk/Control OUT/SETUP
1076
Figure 346. Bulk/Control in Transactions
1080
Figure 347. Normal Interrupt out
1083
Figure 348. Normal Interrupt in
1088
Figure 349. Isochronous out Transactions
1090
Figure 350. Isochronous in Transactions
1093
Device Programming Model
1094
Figure 351. Receive FIFO Packet Read
1097
Figure 352. Processing a SETUP Packet
1099
Figure 353. Bulk out Transaction
1106
Worst Case Response Time
1115
Figure 354. TRDT Max Timing Case
1116
OTG Programming Model
1117
Figure 355. A-Device SRP
1117
Figure 356. B-Device SRP
1118
Figure 357. A-Device HNP
1119
Figure 358. B-Device HNP
1121
Debug Support (DBG)
1123
Overview
1123
Reference Arm® Documentation
1124
SWJ Debug Port (Serial Wire and JTAG)
1124
Mechanism to Select the JTAG-DP or the SW-DP
1125
Pinout and Debug Port Pins
1125
Figure 360. SWJ Debug Port
1125
SWJ Debug Port Pins
1126
Flexible SWJ-DP Pin Assignment
1126
Table 209. SWJ Debug Port Pins
1126
Table 210. Flexible SWJ-DP Pin Assignment
1126
Internal Pull-Up and Pull-Down on JTAG Pins
1127
Using Serial Wire and Releasing the Unused Debug Pins as Gpios
1128
JTAG TAP Connection
1128
Figure 361. JTAG TAP Connections
1129
ID Codes and Locking Mechanism
1130
MCU Device ID Code
1130
Boundary Scan TAP
1130
Cortex
1131
Cortex ® -M4 with FPU JEDEC-106 ID Code
1131
JTAG Debug Port
1131
Table 211. JTAG Debug Port Data Registers
1131
Table 212. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]
1132
SW Debug Port
1133
SW Protocol Introduction
1133
SW Protocol Sequence
1133
Table 213. Packet Request (8-Bits)
1133
SW-DP State Machine (Reset, Idle States, ID Code)
1134
DP and AP Read/Write Accesses
1134
Table 214. ACK Response (3 Bits)
1134
Table 215. DATA Transfer (33 Bits)
1134
SW-DP Registers
1135
Table 216. SW-DP Registers
1135
SW-AP Registers
1136
AHB-AP (AHB Access Port) - Valid for both JTAG-DP and SW-DP
1136
Table 217. Cortex ® -M4 with FPU AHB-AP Registers
1136
Core Debug
1137
Table 218. Core Debug Registers
1137
Capability of the Debugger Host to Connect under System Reset
1138
FPB (Flash Patch Breakpoint)
1138
DWT (Data Watchpoint Trigger)
1139
ITM (Instrumentation Trace Macrocell)
1139
General Description
1139
Time Stamp Packets, Synchronization and Overflow Packets
1139
Table 219. Main ITM Registers
1140
ETM (Embedded Trace Macrocell)
1141
General Description
1141
Signal Protocol, Packet Types
1141
Main ETM Registers
1141
Configuration Example
1142
MCU Debug Component (DBGMCU)
1142
Debug Support for Low-Power Modes
1142
Table 220. Main ETM Registers
1142
Debug Support for Timers, Watchdog, Bxcan and I
1143
1143
1143
Debug MCU Configuration Register
1143
Debug MCU APB1 Freeze Register (DBGMCU_APB1_FZ)
1144
Debug MCU APB2 Freeze Register (DBGMCU_APB2_FZ)
1146
TPIU (Trace Port Interface Unit)
1146
Introduction
1146
Figure 362. TPIU Block Diagram
1147
TRACE Pin Assignment
1148
Table 221. Asynchronous TRACE Pin Assignment
1148
Table 222. Synchronous TRACE Pin Assignment
1148
TPUI Formatter
1149
Table 223. Flexible TRACE Pin Assignment
1149
TPUI Frame Synchronization Packets
1150
Transmission of the Synchronization Frame Packet
1150
Synchronous Mode
1150
Asynchronous Mode
1151
TRACECLKIN Connection
1151
TPIU Registers
1151
Table 224. Important TPIU Registers
1151
30.17.10 Example of Configuration
1152
DBG Register Map
1153
Table 225. DBG Register Map and Reset Values
1153
Device Electronic Signature
1154
Unique Device ID Register (96 Bits)
1154
Flash Size
1155
Package Data Register
1155
Revision History
1157
Table 148. Error Calculation for Programmed Baud Rates at F
1157
Table 149. Error Calculation for Programmed Baud Rates at F PCLK = 100 Mhz or F PCLK = 50 Mhz
1157
Table 226. Document Revision History
1157
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ST STM32F412 Specifications
General
Brand
ST
Model
STM32F412
Category
Microcontrollers
Language
English
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