ST STM32F412 User Manual

Reset and clock control (RCC) for STM32F412xx RM0402
128/1163 RM0402 Rev 6
6.3.4 RCC clock interrupt register (RCC_CIR)
Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. CSSC Res.
PLLI2S
RDYC
PLL
RDYC
HSE
RDYC
HSI
RDYC
LSE
RDYC
LSI
RDYC
w w www w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res.
PLLI2S
RDYIE
PLL
RDYIE
HSE
RDYIE
HSI
RDYIE
LSE
RDYIE
LSI
RDYIE
CSSF Res.
PLLI2S
RDYF
PLL
RDYF
HSE
RDYF
HSI
RDYF
LSE
RDYF
LSI
RDYF
rw rw rw rw rw rw r r r r r r r
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 CSSC: Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Bit 22 Reserved, must be kept at reset value.
Bit 21 PLLI2SRDYC: PLLI2S ready interrupt clear
This bit is set by software to clear the PLLI2SRDYF flag.
0: No effect
1: PLLI2SRDYF cleared
Bit 20 PLLRDYC: Main PLL(PLL) ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: PLLRDYF cleared
Bit 19 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: HSERDYF cleared
Bit 18 HSIRDYC: HSI ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: HSIRDYF cleared
Bit 17 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
Bit 16 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared

ST STM32F412 Specifications

General

Brand	ST
Model	STM32F412
Category	Microcontrollers
Language	English