ST STM32F412 - System and Memory Overview; System Architecture; Figure 1. System Architecture

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RM0402 System and memory overview
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2 System and memory overview
2.1 System architecture
In STM32F412xx, the main system consists of 32-bit multilayer AHB bus matrix that
interconnects:
• Six masters:
–Cortex
®
-M4 with FPU core I-bus, D-bus and S-bus
– DMA1 memory bus
– DMA2 memory bus
– DMA2 peripheral bus
• Six slaves:
– Internal Flash memory ICode bus
– Internal Flash memory DCode bus
– Main internal SRAM
– AHB1 peripherals including AHB to APB bridges and APB peripherals
– AHB2 peripherals
– FSMC / QuadSPI
The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. This
architecture is shown in
Figure 1.
Figure 1. System architecture
MSv37276V1
ARM
Cortex-M4
GP
DMA1
GP
DMA2
Flash
Up to 1MB
SRAM1
256 KB
Bus matrix-S
S0 S1 S2 S3 S4 S5
ICODE
DCODE
ACCEL
M0
M1
M2
I-bus D-bus S-bus DMA_PI DMA_MEM1 DMA_MEM2 DMA_P2
AHB
periph. 1
M3
APB1
APB2
AHB
periph. 2
M4
FSMC external
MemCtrl/
QuadSPI
M5