ST STM32F412 User Manual

RM0402 Rev 6 161/1163
RM0402 Reset and clock control (RCC) for STM32F412xx
166
6.3.24 RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)
Address offset: 0x8C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKDFSD
M1SEL
Res. Res. I2S2RC[1:0] I2S1RC[1:0] TIMPRE Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKDFSD
M1ASEL
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw
Bit 31 CKDFSDMSEL: DFSDM1 Kernel clock selection.
0: APB2 clock used as Kernel clock
1: System clock used as Kernel clock
Bits 30:29 Reserved, must be kept at reset value.
Bits 28:27 I2S2SRC[1:0]: I2S APB2 clocks source selection (I2S1/4/5)
Set and reset by software.
These bits should be written when the PLL and PLLI2S are disabled.
00: I2S APB2 clock frequency = f(
PLLI2S_R
)
01: I2S APB2 clock frequency = external I2S clock from pads - alternate function input
frequency
10: I2S APB2 clock frequency = f(
PLL_R
)
11: I2S APB2 clock frequency = HSI/HSE depending on PLLSRC (PLLCFGR(22))
Bits 26:25 I2S1SRC[1:0]: I2S APB1 clocks source selection (I2S2/3)
Set and reset by software to control the frequency of the APB1 I2S clock.
These bits should be written when the PLL and PLLI2S are disabled.
00: I2S APB1 clock frequency = f(
PLLI2S_R
)
01: I2S APB1 clock frequency = external I2S clock from pads - alternate function input
frequency
10: I2S APB1 clock frequency = f(
PLL_R
)
11: I2S APB1 clock frequency = HSI/HSE depending on PLLSRC (PLLCFGR(22))
Bit 24 TIMPRE: Timers clocks prescalers selection
Set and reset by software to control the clock frequency of all the timers connected to APB1
and APB2 domain.
0: If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a
division factor of 1, TIMxCLK = PCLKx. Otherwise, the timer clock frequencies are set to
twice to the frequency of the APB domain to which the timers are connected:
TIMxCLK = 2xPCLKx.
1:If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a
division factor of 1, 2, or 4, TIMxCLK = HCKL. Otherwise, the timer clock frequencies are set
to four times to the frequency of the APB domain to which the timers are connected:
TIMxCLK = 4xPCLKx.

ST STM32F412 Specifications

General

Brand	ST
Model	STM32F412
Category	Microcontrollers
Language	English