ST STM32F412 User Manual

RM0402 Rev 6 163/1163
RM0402 Reset and clock control (RCC) for STM32F412xx
166
6.3.26 RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR2)
Address offset: 0x94
Reset value: 0x0000 0000
This register allows to enable or disable the clock gating for the specified IPs.
Bit 2
CM4DBG_CKEN: Cortex M4 ETM clock enable
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
Bit 1
AHB2APB2_CKEN: AHB to APB2 Bridge clock enable
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
Bit 0
AHB2APB1_CKEN: AHB to APB1 Bridge clock enable
0: the clock gating is enabled
1: the clock gating is disabled, the clock is always enabled.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res.
SDIO
SEL
CK48M
SEL
Res.
I2CFMP1
SEL[1:0]
Res. Res. Res. Res. Res. Res.
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Bits 31:29 Reserved, must be kept at reset value.
Bit 28 CKSDIOSEL: SDIO clock selection.
0: CK_48MHz (see CK48MSEL bit definition)
1: clock system
Bit 27 CK48MSEL: SDIO/USBFS clock selection.
0: f(
PLL_Q
)
1: f(
PLLI2S_Q
)
Bits 26:24 Reserved, must be kept at reset value.
Bits 23:22 I2CFMP1SEL[1:0]: I2CFMP1 kernel clock source selection
00: APB clock selected as I2CFMP1 clock
01: System clock selected as I2CFMP1 clock
10: HSI clock selected as I2CFMP1 clock
11: APB clock selected as I2CFMP1 (same as “00”)
Bits 21: 0 Reserved, must be kept at reset value.

ST STM32F412 Specifications

General

Brand	ST
Model	STM32F412
Category	Microcontrollers
Language	English