Advanced-control timers (TIM1&TIM8) RM0402
456/1163 RM0402 Rev 6
2. Configure the channel 1 as follows, to detect rising edges on TI:
– IC1F=0000: no filter.
– The capture prescaler is not used for triggering and does not need to be
configured.
– CC1S=01 in TIMx_CCMR1 register to select only the input capture source
– CC1P=0 and CC1NP=’0’ in TIMx_CCER register to validate the polarity (and
detect rising edge only).
3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.
Figure 124. Control circuit in external clock mode 2 + trigger mode
16.3.20 Timer synchronization
The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 17.3.15: Timer synchronization on page 516 for details.
16.3.21 Debug mode
When the microcontroller enters debug mode (Cortex
®
-M4 with FPU core halted), the TIMx
counter either continues to work normally or stops, depending on DBG_TIMx_STOP
configuration bit in DBG module. For more details, refer to
Section 30.16.2: Debug support
for timers, watchdog, bxCAN and I
2
C.
MS33110V1
34 35 36
TIF
Counter register
Counter clock = CK_CNT = CK_PSC
ETR
CEN/CNT_EN
TI1
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