Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit-
772/1163 RM0402 Rev 6
1. 0.5 stop bit (reception in Smartcard mode): No sampling is done for 0.5 stop bit. As
a consequence, no framing error and no break frame can be detected when 0.5 stop bit
is selected.
2. 1 stop bit: Sampling for 1 stop Bit is done on the 8
th
, 9
th
and 10
th
samples.
3. 1.5 stop bits (Smartcard mode): When transmitting in smartcard mode, the device
must check that the data is correctly sent. Thus the receiver block must be enabled (RE
=1 in the USART_CR1 register) and the stop bit is checked to test if the smartcard has
detected a parity error. In the event of a parity error, the smartcard forces the data
signal low during the sampling - NACK signal-, which is flagged as a framing error.
Then, the FE flag is set with the RXNE at the end of the 1.5 stop bit. Sampling for 1.5
stop bits is done on the 16
th
, 17
th
and 18
th
samples (1 baud clock period after the
beginning of the stop bit). The 1.5 stop bit can be decomposed into two parts: one 0.5
baud clock period during which nothing happens, followed by 1 normal stop bit period
during which sampling occurs halfway through. Refer to
Section 25.4.11 for more
details.
4. 2 stop bits: Sampling for 2 stop bits is done on the 8
th
, 9
th
and 10
th
samples of the first
stop bit. If a framing error is detected during the first stop bit the framing error flag will
be set. The second stop bit is not checked for framing error. The RXNE flag will be set
at the end of the first stop bit.
25.4.4 Fractional baud rate generation
The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as
programmed in the Mantissa and Fraction values of USARTDIV.
Equation 1: Baud rate for standard USART (SPI mode included)
Equation 2: Baud rate in Smartcard, LIN and IrDA modes
USARTDIV is an unsigned fixed point number that is coded on the USART_BRR register.
• When OVER8=0, the fractional part is coded on 4 bits and programmed by the
DIV_fraction[3:0] bits in the USART_BRR register
• When OVER8=1, the fractional part is coded on 3 bits and programmed by the
DIV_fraction[2:0] bits in the USART_BRR register, and bit DIV_fraction[3] must be kept
cleared.
Note: The baud counters are updated to the new value in the baud registers after a write operation
to USART_BRR. Hence the baud rate register value should not be changed during
communication.
How to derive USARTDIV from USART_BRR register values when OVER8=0
Example 1:
If DIV_Mantissa = 0d27 and DIV_Fraction = 0d12 (USART_BRR = 0x1BC), then
Mantissa (USARTDIV) = 0d27
Tx/Rx baud
f
CK
8 2 OVER8–()USARTDIV××
-----------------------------------------------------------------------------------=
Tx/Rx baud
f
CK
16 USARTDIV×
---------------------------------------------=
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