Flexible static memory controller (FSMC) RM0402
246/1163 RM0402 Rev 6
11 Flexible static memory controller (FSMC)
11.1 Introduction
The flexible static memory controller (FSMC) includes one memory controller:
• The NOR/PSRAM memory controller
11.2 FSMC main features
The FSMC functional block makes the interface with: synchronous and asynchronous static
memories. Its main purposes are:
• to translate AHB transactions into the appropriate external device protocol
• to meet the access time requirements of the external memory devices
All external memories share the addresses, data and control signals with the controller.
Each external device is accessed by means of a unique chip select. The FSMC performs
only one access at a time to an external device.
The main features of the FSMC controller are the following:
• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR Flash memory/OneNAND Flash memory
– PSRAM (4 memory banks)
• Interface with parallel LCD modules, supporting Intel 8080 and Motorola 6800 modes.
• Burst mode support for faster access to synchronous devices such as NOR Flash
memory, PSRAM)
• Programmable continuous clock output for asynchronous and synchronous accesses
• 8-,16-bit wide data bus
• Independent chip select control for each memory bank
• Independent configuration for each memory bank
• Write enable and byte lane select outputs for use with PSRAM, SRAM devices
• External asynchronous wait control
• Write FIFO with 16 x32-bit depth
The Write FIFO is common to all memory controllers and consists of:
• a Write Data FIFO which stores the AHB data to be written to the memory (up to 32
bits) plus one bit for the AHB transfer (burst or not sequential mode)
• a Write Address FIFO which stores the AHB address (up to 28 bits) plus the AHB data
size (up to 2 bits). When operating in burst mode, only the start address is stored
except when crossing a page boundary (for PSRAM). In this case, the AHB burst is
broken into two FIFO entries.
The Write FIFO can be disabled by setting the WFDIS bit in the FSMC_BCR1 register.
At startup the FSMC pins must be configured by the user application. The FSMC I/O pins
which are not used by the application can be used for other purposes.
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