ST STM32F412 - Figure 140. Counter Timing Diagram, Internal Clock Divided by 2; Figure 141. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0 X36; Figure 142. Counter Timing Diagram, Internal Clock Divided by N

General-purpose timers (TIM2 to TIM5) RM0402
494/1163 RM0402 Rev 6
Figure 140. Counter timing diagram, internal clock divided by 2
Figure 141. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
Figure 142. Counter timing diagram, internal clock divided by N
MS37343V1
CK_INT
Timerclock = CK_CNT
Counter register
Update event (UEV)
Update interrupt flag (UIF)
CNT_EN
Counter underflow
0003 0002 0001 0000 0001 0002 0003
MS37344V1
0034 0035
CK_INT
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow (cnt_ovf)
Update interrupt flag (UIF)
CNT_EN
0036 0035
MS37345V1
CK_INT
Timerclock = CK_CNT
Counter register
Update event (UEV)
Update interrupt flag (UIF)
Counter underflow
001F20 01