RM0402 Rev 6 275/1163
RM0402 Flexible static memory controller (FSMC)
287
Figure 49. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM)
1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM)
access, they are held low.
Addr[15:0] data data
addr[25:16]
Memory transaction = burst of 4 half words
HCLK
CLK
A[25:16]
NEx
NOE
NWE
High
NADV
NWAIT
(WAITCFG=
0)
A/D[15:0]
1 clock
cycle
1 clock
cycle
(DATLAT + 2)
inserted wait state
Data strobes
ai17723f
CLK cycles
data data
Data strobes
Table 66. FSMC_BCRx bitfields (Synchronous multiplexed read mode)
Bit number Bit name Value to set
31:22 Reserved 0x000
21 WFDIS As needed
20 CCLKEN As needed
19 CBURSTRW No effect on synchronous read
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT 0x0
14 EXTMOD 0x0
13 WAITEN
To be set to 1 if the memory supports this feature, to be kept at 0
otherwise
12 WREN No effect on synchronous read
11 WAITCFG To be set according to memory
10 Reserved 0x0
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