Flexible static memory controller (FSMC) RM0402
248/1163 RM0402 Rev 6
11.4 AHB interface
The AHB slave interface allows internal CPUs and other bus master peripherals to access
the external memories.
AHB transactions are translated into the external device protocol. In particular, if the
selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split
into consecutive 16- or 8-bit accesses. The FSMC chip select (FSMC_NEx) does not toggle
between the consecutive accesses except in case of Access mode D when the Extended
mode is enabled.
The FSMC generates an AHB error in the following conditions:
• When reading or writing to an FSMC bank (Bank 1 to 4) which is not enabled.
• When reading or writing to the NOR Flash bank while the FACCEN bit is reset in the
FSMC_BCRx register.
The effect of an AHB error depends on the AHB master which has attempted the R/W
access:
• If the access has been attempted by the Cortex
®
-M4 with FPU CPU, a hard fault
interrupt is generated.
• If the access has been performed by a DMA controller, a DMA transfer error is
generated and the corresponding DMA channel is automatically disabled.
The AHB clock (HCLK) is the reference clock for the FSMC.
11.4.1 Supported memories and transactions
General transaction rules
The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the
accessed external device has a fixed data width. This may lead to inconsistent transfers.
Therefore, some simple transaction rules must be followed:
• AHB transaction size and memory data size are equal
There is no issue in this case.
• AHB transaction size is greater than the memory size:
In this case, the FSMC splits the AHB transaction into smaller consecutive memory
accesses to meet the external data width. The FSMC chip select (FSMC_NEx) does
not toggle between the consecutive accesses.
• AHB transaction size is smaller than the memory size:
The transfer may or not be consistent depending on the type of external device:
– Accesses to devices that have the byte select feature (SRAM, ROM, PSRAM)
In this case, the FSMC allows read/write transactions and accesses the right data
through its byte lanes NBL[1:0].
Bytes to be written are addressed by NBL[1:0].
All memory bytes are read (NBL[1:0] are driven low during read transaction) and
the useless ones are discarded.
– Accesses to devices that do not have the byte select feature (NOR)
This situation occurs when a byte access is requested to a 16-bit wide Flash
memory. Since the device cannot be accessed in Byte mode (only 16-bit words
can be read/written from/to the Flash memory), Write transactions and Read
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