Digital filter for sigma delta modulators (DFSDM) RM0402
394/1163 RM0402 Rev 6
14.8.13 DFSDM filter x extremes detector maximum register
(DFSDM_FLTxEXMAX)
Address offset: 0x130 + 0x80 * x, (x = 0 to 1)
Reset value: 0x8000 0000
14.8.14 DFSDM filter x extremes detector minimum register
(DFSDM_FLTxEXMIN)
Address offset: 0x134 + 0x80 * x, (x = 0 to 1)
Reset value: 0x7FFF FF00
Bits 11:8 CLRAWHTF[3:0]: Clear the analog watchdog high threshold flag
CLRAWHTF[y]=0: Writing ‘0’ has no effect
CLRAWHTF[y]=1: Writing ‘1’ to position y clears the corresponding AWHTF[y] bit in the
DFSDM_FLTxAWSR register
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 CLRAWLTF[3:0]: Clear the analog watchdog low threshold flag
CLRAWLTF[y]=0: Writing ‘0’ has no effect
CLRAWLTF[y]=1: Writing ‘1’ to position y clears the corresponding AWLTF[y] bit in the
DFSDM_FLTxAWSR register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMAX[23:8]
rs_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r
1514131211109876543210
EXMAX[7:0] Res. Res. Res. Res. Res. Res. EXMAXCH[1:0]
rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r r r
Bits 31:8 EXMAX[23:0]: Extremes detector maximum value
These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx.
EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
Bits 7:2 Reserved, must be kept at reset value.
Bits 1:0 EXMAXCH[1:0]: Extremes detector maximum data channel.
These bits contains information about the channel on which the data is stored into EXMAX[23:0].
Bits are cleared by reading of this register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EXMIN[23:8]
rc_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r
1514131211109876543210
EXMIN[7:0] Res. Res. Res. Res. Res. Res. EXMINCH[1:0]
rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r r r
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