RM0402 Rev 6 785/1163
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver
810
Figure 253. Mute mode using address mark detection
25.4.7 Parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame
length defined by the M bit, the possible USART frame formats are as listed in
Table 152.
Even parity
The parity bit is calculated to obtain an even number of “1s” inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
E.g.: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit in
USART_CR1 = 0).
Odd parity
The parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or
8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
E.g.: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit in
USART_CR1 = 1).
Parity checking in reception
If the parity check fails, the PE flag is set in the USART_SR register and an interrupt is
generated if PEIE is set in the USART_CR1 register. The PE flag is cleared by a software
MSv31155V1
IDLE Addr=0 Data 1 Data 2 IDLE Addr=1 Data 3 Data 4 Addr=2 Data 5
In this example, the current address of the receiver is 1
(programmed in the USART_CR2 register)
RXNE
Non-matching addressMatching address
Non-matching address
MMRQ written to 1
(RXNE was cleared)
RWU
RX
Mute mode Mute modeNormal mode
RXNE RXNE
Table 152. Frame formats
M bit PCE bit USART frame
(1)
1. Legends: SB: start bit, STB: stop bit, PB: parity bit.
0 0 | SB | 8 bit data | STB |
0 1 | SB | 7-bit data | PB | STB |
1 0 | SB | 9-bit data | STB |
1 1 | SB | 8-bit data PB | STB |
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