ST STM32F412 - I 2 C Main Features

Inter-integrated circuit (I
2
C) interface RM0402
724/1163 RM0402 Rev 6
24.2 I
2
C main features
• Parallel-bus/I
2
C protocol converter
• Multimaster capability: the same interface can act as Master or Slave
• I
2
C Master features:
– Clock generation
– Start and Stop generation
• I
2
C Slave features:
– Programmable I
2
C Address detection
– Dual Addressing Capability to acknowledge 2 slave addresses
– Stop bit detection
• Generation and detection of 7-bit/10-bit addressing and General Call
• Supports different communication speeds:
– Standard Speed (up to 100 kHz)
– Fast Speed (up to 400 kHz)
• Analog noise filter
• Programmable digital noise filter
• Status flags:
– Transmitter/Receiver mode flag
– End-of-Byte transmission flag
–I
2
C busy flag
• Error flags:
– Arbitration lost condition for master mode
– Acknowledgment failure after address/ data transmission
– Detection of misplaced start or stop condition
– Overrun/Underrun if clock stretching is disabled
• 2 Interrupt vectors:
– 1 Interrupt for successful address/ data communication
– 1 Interrupt for error condition
• Optional clock stretching
• 1-byte buffer with DMA capability
• Configurable PEC (packet error checking) generation or verification:
– PEC value can be transmitted as last byte in Tx mode
– PEC error checking for last received byte
• SMBus 2.0 Compatibility:
– 25 ms clock low timeout delay
– 10 ms master cumulative clock low extend time
– 25 ms slave cumulative clock low extend time
– Hardware PEC generation/verification with ACK control
– Address Resolution Protocol (ARP) supported
• PMBus Compatibility